Inventor

David B. Witt

Inventor

Austin, TX, US

Overview

1988–2006

Patent span

Physics

Primary field (CPC G)

Patents· 106 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing92%

G11CStatic stores2%

H03KPulse technique2%

B60LPropulsion of electrically-propelled vehicles1%

G01RMeasuring electric variables1%

H01CResistors1%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use1%

Y02TClimate change mitigation technologies related to transportation1%

PatentTitleYear

7,120,781'General purpose register file architecture for aligned simd'2006 6,918,028'Pipelined processor including a loosely coupled side pipe'2005 6,584,556'Modulo address generation method and apparatus'2003 6,553,482'Universal dependency vector/queue entry'2003 6,505,292'Processor including efficient fetch mechanism for L0 and L1 caches'2003 6,457,117'Processor configured to predecode relative control transfer instructions and replace displacements therein with a target address'2002 6,446,181'System having a configurable cache/SRAM memory'2002 6,404,324'Resistive component for use with short duration, high-magnitude currents'2002 6,393,549'Instruction alignment unit for routing variable byte-length instructions'2002 6,393,546'Physical rename register for efficiently storing floating point, integer, condition code, and multimedia values'2002 6,381,689'Line-oriented reorder buffer configured to selectively store a memory operation result in one of the plurality of reorder buffer storage locations corresponding to the executed instruction'2002 6,367,001'Processor including efficient fetch mechanism for L0 and L1 caches'2002 6,347,369'Method and circuit for single cycle multiple branch history table access'2002 6,332,191'System for canceling speculatively fetched instructions following a branch mis-prediction in a microprocessor'2001 6,332,187'Cumulative lookahead to eliminate chained dependencies'2001 6,321,326'Prefetch instruction specifying destination functional unit and read/write access mode'2001 6,308,259'Instruction queue evaluating dependency vector in portions during different clock phases'2001 6,298,423'High performance load/store functional unit and data cache'2001 6,292,884'Reorder buffer employing last in line indication'2001 6,279,101'Instruction decoder/dispatch'2001 6,266,763'Physical rename register for efficiently storing floating point, integer, condition code, and multimedia values'2001 6,266,752'Reverse TLB for providing branch target address in a microprocessor having a physically-tagged cache'2001 6,256,721'Register renaming in which moves are accomplished by swapping tags'2001 6,256,728'Processor configured to selectively cancel instructions from its pipeline responsive to a predicted-taken short forward branch instruction'2001 6,247,106'Processor configured to map logical register numbers to physical register numbers using virtual register numbers'2001 6,240,484'Linearly addressable microprocessor cache'2001 6,240,503'Cumulative lookahead to eliminate chained dependencies'2001 6,237,082'Reorder buffer configured to allocate storage for instruction results corresponding to predefined maximum number of concurrently receivable instructions independent of a number of instructions received'2001 6,230,262'Processor configured to selectively free physical registers upon retirement of instructions'2001 6,219,784'Processor with N adders for parallel target addresses calculation'2001 6,212,622'Mechanism for load block on store address generation'2001 6,212,623'Universal dependency vector/queue entry'2001 6,202,139'Pipelined data cache with multiple ports and processor with load/store unit selecting only load or store operations for concurrent processing'2001 6,199,154'Selecting cache to fetch in multi-level cache system based on fetch address source and pre-fetching additional data to the cache for future access'2001 6,192,462'Superscalar microprocessor including a load/store unit, decode units and a reorder buffer to detect dependencies between access to a stack cache and a data cache'2001 6,189,068'Superscalar microprocessor employing a data cache capable of performing store accesses in a single clock cycle'2001 6,189,087'Superscalar instruction decoder including an instruction queue'2001 6,167,506'Replacing displacement in control transfer instruction with encoding indicative of target address, including offset and target cache line location'2000 6,161,167'Fully associate cache employing LRU groups for cache replacement and mechanism for selecting an LRU group'2000 6,157,986'Fast linear tag validation unit for use in microprocessor'2000 6,141,747'System for store to load forwarding of individual bytes from separate store buffer entries to form a single load word'2000 6,134,649'Control transfer indication in predecode which identifies control transfer instruction and an alternate feature of an instruction'2000 6,134,651'Reorder buffer employed in a microprocessor to store instruction results having a plurality of entries predetermined to correspond to a plurality of functional units'2000 6,122,727'Symmetrical instructions queue for high clock frequency scheduling'2000 6,122,656'Processor configured to map logical register numbers to physical register numbers using virtual register numbers'2000 6,119,223'Map unit having rapid misprediction recovery'2000 6,112,293'Processor configured to generate lookahead results from operand collapse unit and for inhibiting receipt/execution of the first instruction based on the lookahead result'2000 6,112,296'Floating point stack manipulation using a register map and speculative top of stack values'2000 6,094,716'Register renaming in which moves are accomplished by swapping rename tags'2000 6,088,789'Prefetch instruction specifying destination functional unit and read/write access mode'2000 6,081,656'Method for deriving a double frequency microprocessor from an existing microprocessor'2000 6,079,003'Reverse TLB for providing branch target address in a microprocessor having a physically-tagged cache'2000 6,079,005'Microprocessor including virtual address branch prediction and current page register to provide page portion of virtual and physical fetch address'2000 6,061,786'Processor configured to select a next fetch address by partially decoding a byte of a control transfer instruction'2000 6,032,251'Computer system including a microprocessor having a reorder buffer employing last in buffer and last in line indications'2000 6,026,482'Recorder buffer and a method for allocating a fixed amount of storage for instruction results independent of a number of concurrently dispatched instructions'2000 6,018,798'Floating point unit using a central window for storing instructions capable of executing multiple instructions in a single clock cycle'2000 6,006,324'High performance superscalar alignment unit'1999 5,991,869'Superscalar microprocessor including a high speed instruction alignment unit'1999 5,987,561'Superscalar microprocessor employing a data cache capable of performing store accesses in a single clock cycle'1999 5,978,907'Delayed update register for an array'1999 5,970,235'Pre-decoded instruction cache and method therefor particularly suitable for variable byte-length instructions'1999 5,946,468'Reorder buffer having an improved future file for storing speculative instruction execution results'1999 5,944,815'Microprocessor configured to execute a prefetch instruction including an access count field defining an expected number of access'1999 5,915,110'Branch misprediction recovery in a reorder buffer having a future file'1999 5,903,741'Method of allocating a fixed reorder buffer storage line for execution results regardless of a number of concurrently dispatched instructions'1999 5,903,910'Method for transferring data between a pair of caches configured to be accessed from different stages of an instruction processing pipeline'1999 5,901,302'Superscalar microprocessor having symmetrical, fixed issue positions each configured to execute a particular subset of instructions'1999 5,878,255'Update unit for providing a delayed update to a branch prediction array'1999 5,878,244'Reorder buffer configured to allocate storage capable of storing results corresponding to a maximum number of concurrently receivable instructions regardless of a number of instructions received'1999 5,878,245'High performance load/store functional unit and data cache'1999 5,875,324'Superscalar microprocessor which delays update of branch prediction information in response to branch misprediction until a subsequent idle clock'1999 5,867,682'High performance superscalar microprocessor including a circuit for converting CISC instructions to RISC operations'1999 5,867,683'Method of operating a high performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations'1999 5,860,104'Data cache which speculatively updates a predicted data cache storage location with store data and subsequently corrects mispredicted updates'1999 5,848,287'Superscalar microprocessor including a reorder buffer which detects dependencies between accesses to a pair of caches'1998 5,835,753'Microprocessor with dynamically extendable pipeline stages and a classifying circuit'1998 5,835,744'Microprocessor configured to swap operands in order to minimize dependency checking logic'1998 5,831,462'Conditional latching mechanism and pipelined microprocessor employing the same'1998 5,832,249'High performance superscalar alignment unit'1998 5,828,869'Microprocessor arranged for synchronously accessing an external memory with a scalable clocking mechanism'1998 5,826,053'Speculative instruction queue and method therefor particularly suitable for variable byte-length instructions'1998 5,819,057'Superscalar microprocessor including an instruction alignment unit with limited dispatch to decode units'1998 5,813,045'Conditional early data address generation mechanism for a microprocessor'1998 5,805,912'Microprocessor arranged to synchronously access an external memory operating at a slower rate than the microproccessor'1998 5,796,973'Method and apparatus for decoding one or more complex instructions into concurrently dispatched simple instructions'1998 5,768,555'Reorder buffer employing last in buffer and last in line bits'1998 5,761,691'Linearly addressable microprocessor cache'1998 5,758,114'High speed instruction alignment unit for aligning variable byte-length instructions according to predecode information in a superscalar microprocessor'1998 5,751,981'High performance superscalar microprocessor including a speculative instruction queue for byte-aligning CISC instructions stored in a variable byte-length format'1998 5,689,672'Pre-decoded instruction cache and method therefor particularly suitable for variable byte-length instructions'1997 5,684,422'Pipelined microprocessor including a high speed single-clock latch circuit'1997 5,664,136'High performance superscalar microprocessor including a dual-pathway circuit for converting cisc instructions to risc operations'1997 5,655,097'High performance superscalar microprocessor including an instruction cache circuit for byte-aligning CISC instructions stored in a variable byte-length format'1997 5,655,098'High performance superscalar microprocessor including a circuit for byte-aligning cisc instructions stored in a variable byte-length format'1997 5,651,125'High performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations'1997 5,630,100'Simulating multi-phase clock designs using a single clock edge based system'1997 5,623,619'Linearly addressable microprocessor cache'1997 5,623,627'Computer memory architecture including a replacement cache'1997 5,357,626'Processing system for providing an in circuit emulator with processor internal state'1994 5,291,070'Microprocessor synchronous timing system'1994 5,247,644'Processing system with improved sequential memory accessing'1993 5,157,780'Master-slave checking system'1992 5,059,818'Self-regulating clock generator'1991 4,882,673'Method and apparatus for testing an integrated circuit including a microprocessor and an instruction cache'1989 4,731,737'High speed intelligent distributed control memory system'1988

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1988–2003Patents assigned to ADVANCED MICRO DEVICES INC (101)· patent assignee history

1988–2006Based in Austin, TX, US· patent location history

2002–2006Patents assigned to ANALOG DEVICES INC (4)· patent assignee history

2002Patents assigned to GEN MOTORS CORP (1)· patent assignee history

2002Patents assigned to INTEL CORP (1)· patent assignee history

2002Based in Fishers, IN, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
ADVANCED MICRO DEVICES INC	101	1988–2003
ANALOG DEVICES INC	4	2002–2006
GEN MOTORS CORP	1	2002
INTEL CORP	1	2002

Locations

Location	Patents	Span
Austin, Texas, US	105	1988–2006
Fishers, IN, US	1	2002