Inventor

Steven C. Avanzino

Inventor

Cupertino, CA, US

Overview

1990–2016

Patent span

Electricity

Primary field (CPC H)

Patents· 127 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1028%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1023%

H10BElectronic memory devices8%

H10NElectric solid-state devices not otherwise provided for8%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%

H10DInorganic electric semiconductor devices4%

G11CStatic stores3%

C09GPolishing compositions3%

C09KMaterials for miscellaneous applications, not provided for elsewhere2%

B24BMachines, devices, or processes for grinding or polishing2%

PatentTitleYear

9,343,666'Damascene metal-insulator-metal (MIM) device with improved scaleability'2016 9,012,299'Metal-insualtor-metal (MIM) device and method of formation thereof'2015 8,828,837'Metal-insulator-metal (MIM) device and method of formation thereof'2014 8,803,120'Diode and resistive memory device structures'2014 8,717,803'Metal-insulator-metal-insulator-metal (MIMIM) memory device'2014 8,445,913'Metal-insulator-metal (MIM) device and method of formation thereof'2013 8,232,175'Damascene metal-insulator-metal (MIM) device with improved scaleability'2012 8,093,698'Gettering/stop layer for prevention of reduction of insulating oxide in metal-insulator-metal device'2012 8,093,680'Metal-insulator-metal-insulator-metal (MIMIM) memory device'2012 8,089,113'Damascene metal-insulator-metal (MIM) device'2012 8,084,770'Test structures for development of metal-insulator-metal (MIM) devices'2011 8,035,099'Diode and resistive memory device structures'2011 7,968,464'Memory device with improved data retention'2011 7,830,015'Memory device with improved data retention'2010 7,790,497'Method to prevent alloy formation when forming layered metal oxides by metal oxidation'2010 7,776,682'Ordered porosity to direct memory element formation'2010 7,706,168'Erase, programming and leakage characteristics of a resistive memory device'2010 7,468,525'Test structures for development of metal-insulator-metal (MIM) devices'2008 7,465,408'Solutions for controlled, selective etching of copper'2008 7,384,800'Method of fabricating metal-insulator-metal (MIM) device with stable data retention'2008 7,306,988'Memory cell and method of making the memory cell'2007 7,307,321'Memory device with improved data retention'2007 7,288,782'Use of Ta-capped metal line to improve formation of memory element films'2007 7,235,867'Semiconductor device with electrically biased die edge seal'2007 7,232,765'Utilization of a Ta-containing cap over copper to facilitate concurrent formation of copper vias and memory element structures'2007 7,220,642'Protection of active layers of memory cells during processing of other elements'2007 7,157,795'Composite tantalum nitride/tantalum copper capping layer'2007 7,148,144'Method of forming copper sulfide layer over substrate'2006 7,141,482'Method of making a memory cell'2006 7,129,133'Method and structure of memory element plug with conductive Ta removed from sidewall at region of memory element film'2006 7,084,062'Use of Ta-capped metal line to improve formation of memory element films'2006 7,071,564'Composite tantalum capped inlaid copper with reduced electromigration and reduced stress migration'2006 7,035,141'Diode array architecture for addressing nanoscale resistive memory arrays'2006 7,011,762'Metal bridging monitor for etch and CMP endpoint detection'2006 6,989,604'Conformal barrier liner in an integrated circuit interconnect'2006 6,979,903'Integrated circuit with dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers'2005 6,934,032'Copper oxide monitoring by scatterometry/ellipsometry during nitride or BLOK removal in damascene process'2005 6,841,473'Manufacturing an integrated circuit with low solubility metal-conductor interconnect cap'2005 6,836,017'Protection of low-k ILD during damascene processing with thin liner'2004 6,808,591'Model based metal overetch control'2004 6,771,356'Scatterometry of grating structures to monitor wafer stress'2004 6,756,306'Low temperature dielectric deposition to improve copper electromigration performance'2004 6,723,635'Protection low-k ILD during damascene processing with thin liner'2004 6,720,264'Prevention of precipitation defects on copper interconnects during CMP by use of solutions containing organic compounds with silica adsorption and copper corrosion inhibiting properties'2004 6,702,648'Use of scatterometry/reflectometry to measure thin film delamination during CMP'2004 6,699,785'Conductor abrasiveless chemical-mechanical polishing in integrated circuit interconnects'2004 6,684,172'Sensor to predict void free films using various grating structures and characterize fill performance'2004 6,682,978'Integrated circuit having increased gate coupling capacitance'2004 6,657,304'Conformal barrier liner in an integrated circuit interconnect'2003 6,657,303'Integrated circuit with low solubility metal-conductor interconnect cap'2003 6,642,145'Method of manufacturing an integrated circuit with a dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers'2003 6,624,642'Metal bridging monitor for etch and CMP endpoint detection'2003 6,599,827'Methods of forming capped copper interconnects with improved electromigration resistance'2003 6,596,637'Chemically preventing Cu dendrite formation and growth by immersion'2003 6,593,632'Interconnect methodology employing a low dielectric constant etch stop layer'2003 6,562,185'Wafer based temperature sensors for characterizing chemical mechanical polishing processes'2003 6,548,336'Planarization of a polysilicon layer surface by chemical mechanical polish to improve lithography and silicide formation'2003 6,530,997'Use of gaseous silicon hydrides as a reducing agent to remove re-sputtered silicon oxide'2003 6,528,409'Interconnect structure formed in porous dielectric material with minimized degradation and electromigration'2003 6,525,428'Graded low-k middle-etch stop layer for dual-inlaid patterning'2003 6,518,185'Integration scheme for non-feature-size dependent cu-alloy introduction'2003 6,506,677'Method of forming capped copper interconnects with reduced hillock formation and improved electromigration resistance'2003 6,503,418'Ta barrier slurry containing an organic additive'2003 6,500,754'Anneal hillock suppression method in integrated circuit interconnects'2002 6,500,743'Method of copper-polysilicon T-gate formation'2002 6,469,385'Integrated circuit with dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers'2002 6,465,156'Method for mitigating formation of silicon grass'2002 6,454,916'Selective electroplating with direct contact chemical polishing'2002 6,433,379'Tantalum anodization for in-laid copper metallization capacitor'2002 6,432,822'Method of improving electromigration resistance of capped Cu'2002 6,422,918'Chemical-mechanical polishing of photoresist layer'2002 6,417,100'Annealing ambient in integrated circuit interconnects'2002 6,413,869'Dielectric protected chemical-mechanical polishing in integrated circuit interconnects'2002 6,410,443'Method for removing semiconductor ARC using ARC CMP buffing'2002 6,403,474'Controlled anneal conductors for integrated circuit interconnects'2002 6,352,817'Methodology for mitigating formation of t-tops in photoresist'2002 6,350,687'Method of fabricating improved copper metallization including forming and removing passivation layer before forming capping film'2002 6,346,466'Planarization of a polysilicon layer surface by chemical mechanical polish to improve lithography and silicide formation'2002 6,332,989'Slurry for chemical mechanical polishing of copper'2001 6,326,305'Ceria removal in chemical-mechanical polishing of integrated circuits'2001 6,319,833'Chemically preventing copper dendrite formation and growth by spraying'2001 6,319,834'Method and apparatus for improved planarity metallization by electroplating and CMP'2001 6,291,339'Bilayer interlayer dielectric having a substantially uniform composite interlayer dielectric constant over pattern features of varying density and method of making the same'2001 6,268,285'Method of removing plasma etch damage to pre-silicidized surfaces by wet silicon etch'2001 6,265,273'Method of forming rectangular shaped spacers'2001 6,235,453'Low-k photoresist removal process'2001 6,232,635'Method to fabricate a high coupling flash cell with less silicide seam problem'2001 6,218,290'Copper dendrite prevention by chemical removal of dielectric'2001 6,211,071'Optimized trench/via profile for damascene filling'2001 6,207,569'Prevention of Cu dendrite formation and growth'2001 6,197,690'Chemically preventing Cu dendrite formation and growth by double sided scrubbing'2001 6,184,141'Method for multiple phase polishing of a conductive layer in a semidonductor wafer'2001 6,177,349'Preventing Cu dendrite formation and growth'2001 6,169,034'Chemically removable Cu CMP slurry abrasive'2001 6,162,727'Chemical treatment for preventing copper dendrite formation and growth'2000 6,153,933'Elimination of residual materials in a multiple-layer interconnect structure'2000 6,143,656'Slurry for chemical mechanical polishing of copper'2000 6,140,239'Chemically removable Cu CMP slurry abrasive'2000 6,137,126'Method to reduce gate-to-local interconnect capacitance using a low dielectric constant material for LDD spacer'2000 6,121,150'Sputter-resistant hardmask for damascene trench/via formation'2000 6,121,149'Optimized trench/via profile for damascene filling'2000 6,117,782'Optimized trench/via profile for damascene filling'2000 6,117,781'Optimized trench/via profile for damascene processing'2000 6,074,949'Method of preventing copper dendrite formation and growth'2000 6,051,882'Subtractive dual damascene semiconductor device'2000 6,048,802'Selective nonconformal deposition for forming low dielectric insulation between certain conductive lines'2000 6,017,463'Point of use mixing for LI/plug tungsten polishing slurry to improve existing slurry'2000 5,990,557'Bias plasma deposition for selective low dielectric insulation'1999 5,955,786'Semiconductor device using uniform nonconformal deposition for forming low dielectric constant insulation between certain conductive lines'1999 5,916,855'Chemical-mechanical polishing slurry formulation and method for tungsten and titanium thin films'1999 5,837,618'Uniform nonconformal deposition for forming low dielectric constant insulation between certain conductive lines'1998 5,795,823'Self aligned via dual damascene'1998 5,776,834'Bias plasma deposition for selective low dielectric insulation'1998 5,770,519'Copper reservoir for reducing electromigration effects associated with a conductive via in a semiconductor device'1998 5,705,430'Dual damascene with a sacrificial via fill'1998 5,691,573'Composite insulation with a dielectric constant of less than 3 in a narrow space separating conductive lines'1997 5,691,238'Subtractive dual damascene'1997 5,686,354'Dual damascene with a protective mask for via etching'1997 5,665,199'Methodology for developing product-specific interlayer dielectric polish processes'1997 5,662,769'Chemical solutions for removing metal-compound contaminants from wafers after CMP and the method of wafer cleaning'1997 5,646,448'Copper pellet for reducing electromigration effects associated with a conductive via in a semiconductor device'1997 5,639,691'Copper pellet for reducing electromigration effects associated with a conductive via in a semiconductor device'1997 5,614,765'Self aligned via dual damascene'1997 5,382,547'Void free oxide fill for interconnect spaces'1995 5,116,778'Dopant sources for CMOS device'1992 4,962,064'Method of planarization of topologies in integrated circuit structures'1990 4,954,459'Method of planarization of topologies in integrated circuit structures'1990

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1990–2008Patents assigned to ADVANCED MICRO DEVICES INC (99)· patent assignee history

1990–2016Based in Cupertino, CA, US· patent location history

2006–2015Patents assigned to SPANSION LLC (26)· patent assignee history

2011–2016Patents assigned to AVANZINO STEVEN (9)· patent assignee history

2011–2016Patents assigned to PANGRLE SUZETTE K (8)· patent assignee history

2011–2016Patents assigned to RATHOR MANUJ (8)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
ADVANCED MICRO DEVICES INC	99	1990–2008
SPANSION LLC	26	2006–2015
AVANZINO STEVENself	9	2011–2016
PANGRLE SUZETTE K	8	2011–2016
RATHOR MANUJ	8	2011–2016

Locations

Location	Patents	Span
Cupertino, California, US	127	1990–2016