Inventor
William H. Radke
Inventor
Los Gatos, CA, US
Overview
Patents· 189 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing39%
G11CStatic stores33%
H03MCoding11%
G09GArrangements or circuits for control of indicating devices using static means to present variable information4%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use3%
H05KPrinted circuits2%
G06TImage data processing or generation, in general2%
H04LTransmission of digital information, e.g. telegraphic communication2%
B32BLayered products, i.e. products built-up of strata of flat or non-flat, e.g. cellular or honeycomb, form1%
F16LPipes1%
PatentTitleYear
10,998,923Stopping criteria for layered iterative error correction202110,891,187Memory devices having differently configured blocks of memory cells202110,891,188Memory devices having differently configured blocks of memory cells202110,804,243Dual-sided memory module with channels aligned in opposition202010,762,003State change in systems having devices coupled in a chained configuration202010,664,411Chained bus memory device202010,409,673Memory devices having differently configured blocks of memory cells201910,217,721Dual-sided memory module with channels aligned in opposition201910,193,577Stopping criteria for layered iterative error correction201910,089,250State change in systems having devices coupled in a chained configuration201810,082,957Dual-ported PCI express-based storage cartridge including single-ported storage controllers201810,068,655Inferring threshold voltage distributions associated with memory cells via interpolation20189,983,928Apparatuses and methods including error correction code organization20189,929,967'Packet deconstruction/reconstruction and link-control'20189,901,010'High density server storage unit'20189,891,675'Systems and methods for packaging high density SSDs'20189,811,258'Methods for controlling host memory access with memory devices and systems'20179,779,828'Inferring threshold voltage distributions associated with memory cells via interpolation'20179,766,830'Power consumption control'20179,702,305'Multiple engine sequencer'20179,654,141'Memory devices and systems configured to adjust a size of an ECC coverage area'20179,646,683'Memory apparatus, systems, and methods'20179,645,940'Apparatus and method for accessing a non-volatile memory blade using multiple controllers in a non-volatile memory based storage device'20179,606,885'Chained bus method'20179,600,038'Systems and methods for securing high density SSDs'20179,594,676'Configuring and reconfiguring blocks of memory cells to store user data and ECC data'20179,588,697'Host controller'20179,585,290'High capacity storage unit'20179,552,257'Memory cell coupling compensation'20179,520,183'Threshold voltage compensation in a memory'20169,507,529'Apparatus and method for routing information in a non-volatile memory-based storage device'20169,471,425'Data conditioning to improve flash memory reliability'20169,455,043'Dynamic program window determination in a memory device'20169,442,796'Memory controller supporting rate-compatible punctured codes'20169,390,004'Hybrid memory management'20169,368,163'Power consumption control'20169,361,996'Inferring threshold voltage distributions associated with memory cells via interpolation'20169,349,441'Fractional bits in memory cells'20169,342,371'Boot partitions in memory devices and systems'20169,336,086'Apparatuses and methods including error correction code organization'20169,336,134'Apparatus and method for accessing a non-volatile memory blade using multiple controllers in a non-volatile memory based storage device'20169,318,220'Memory cell coupling compensation'20169,304,557'Systems and methods for packaging high density SSDS'20169,305,659'Dynamic program window determination in a memory device'20169,301,402'High density server storage unit'20169,293,214'Determining and using soft data in memory devices and systems'20169,269,450'Methods, devices, and systems for adjusting sensing voltages in devices'20169,262,261'Memory devices facilitating differing depths of error detection and/or error correction coverage'20169,235,343'State change in systems having devices coupled in a chained configuration'20169,229,802'Non-systematic coded error correction'20169,230,660'Data modulation for groups of memory cells'20169,229,855'Apparatus and method for routing information in a non-volatile memory-based storage device'20169,197,251'Method and apparatus for reading data from non-volatile memory'20159,177,651'Programming methods and memories'20159,177,659'Determining and using soft data in memory devices and systems'20159,171,633'Memory and sense parameter determination methods'20159,165,681'Applying a voltage-delay correction to a non-defective memory block that replaces a defective memory block based on the actual location of the non-defective memory block'20159,152,546'Fault-tolerant non-volatile integrated circuit memory'20159,147,476'Programming methods and memories'20159,129,684'Dynamic program window determination in a memory device'20159,116,822'Stopping criteria for layered iterative error correction'20159,110,832'Object oriented memory in solid state devices'20159,087,594'Memory apparatus, systems, and methods'20159,075,765'State change in systems having devices coupled in a chained configuration'20159,063,875'Error recovery storage along a memory string'20159,043,506'Host controller'20159,037,842'Booting in systems having devices coupled in a chained configuration'20159,030,870'Threshold voltage compensation in a multilevel memory'20158,964,465'Fractional bits in memory cells'20158,966,352'Memory controller supporting rate-compatible punctured codes and supporting block codes'20158,954,818'Error detection and correction scheme for a memory device'20158,954,825'Apparatuses and methods including error correction code organization'20158,943,387'Programming management data for a memory'20158,938,657'Data and error correction code mixing device and method'20158,934,306'Memory and sense parameter determination methods'20158,918,600'Methods for controlling host memory access with memory devices and systems'20148,902,648'Dynamic program window determination in a memory device'20148,902,653'Memory devices and configuration methods for a memory device'20148,848,453'Inferring threshold voltage distributions associated with memory cells via interpolation'20148,848,478'Power consumption control'20148,830,762'Methods, devices, and systems for dealing with threshold voltage change in memory devices'20148,797,803'Methods, devices, and systems for adjusting sensing voltages in devices'20148,782,493'Correcting data in a memory'20148,762,629'Data conditioning to improve flash memory reliability'20148,762,703'Boot partitions in memory devices and systems'20148,751,860'Object oriented memory in solid state devices'20148,751,733'Hybrid memory management'20148,725,937'Fault-tolerant non-volatile integrated circuit memory'20148,719,680'Method and apparatus for reading data from non-volatile memory'20148,713,401'Error recovery storage along a memory string'20148,711,617'Data modulation for groups of memory cells'20148,713,385'Error scanning in flash memory'20148,704,840'Memory system having multiple address allocation formats and method for use thereof'20148,705,299'Replacing defective memory blocks in response to external addresses'20148,687,431'Programming methods and memories'20148,681,547'Memory cell coupling compensation'20148,670,272'Memory with weighted multi-page read'20148,661,312'Error detection and correction scheme for a memory device'20148,635,510'Non-systematic coded error correction'20148,631,302'Data and error correction code mixing device and method'20148,630,182'Packet deconstruction/reconstruction and link-control'20148,627,180'Memory controller ECC'20148,599,637'Advanced detection of memory device removal, and methods, devices and connectors'20138,576,632'Methods, devices, and systems for dealing with threshold voltage change in memory devices'20138,578,070'Host controller'20138,566,675'Data handling'20138,560,735'Chained bus method and device'20138,543,802'Booting in systems having devices coupled in a chained configuration'20138,539,117'State change in systems having devices coupled in a chained configuration'20138,531,877'Fractional bits in memory cells'20138,510,634'Methods of data handling'20138,499,229'Method and apparatus for reading data from flash memory'20138,468,415'Error recovery storage along a memory string'20138,458,564'Programming management data for a memory'20138,451,664'Determining and using soft data in memory devices and systems'20138,446,787'Replacing defective memory blocks in response to external addresses'20138,446,420'Memory system and method for improved utilization of read and write bandwidth of a graphics processing system'20138,429,391'Boot partitions in memory devices and systems'20138,402,178'Device to device flow control within a chain of devices'20138,381,076'Variable sector-count ECC'20138,359,514'Data and error correction code mixing device and method'20138,358,542'Methods, devices, and systems for adjusting sensing voltages in devices'20138,356,216'Error scanning in flash memory'20138,331,143'Memory with multi-page read'20128,327,040'Host controller'20128,327,245'Memory controller supporting rate-compatible punctured codes'20128,305,809'Methods, devices, and systems for dealing with threshold voltage change in memory devices'20128,296,510'Hybrid memory management'20128,295,109'Replacing defective columns of memory cells in response to external addresses'20128,296,692'Read strobe feedback in a memory system'20128,281,061'Data conditioning to improve flash memory reliability'20128,271,697'State change in systems having devices coupled in a chained configuration'20128,254,180'Methods of operating memories including characterizing memory cell signal lines'20128,245,100'Error recovery storage along a nand-flash string'20128,245,024'Booting in systems having devices coupled in a chained configuration'20128,239,725'Data storage with an outer block code and a stream-based inner code'20128,238,244'Packet deconstruction/reconstruction and link-control'20128,234,439'Fault-tolerant non-volatile integrated circuit memory'20128,225,052'Methods for controlling host memory access with memory devices and systems'20128,209,447'Device to device flow control within a chain of devices'20128,194,086'Memory system and method for improved utilization of read and write bandwidth of a graphics processing system'20128,189,387'Flash memory with multi-bit read'20128,189,420'Advanced detection of memory device removal, and methods, devices and connectors'20128,125,826'Fractional bits in memory cells'20128,122,321'Methods of data handling'20128,095,835'Error scanning in flash memory'20128,077,515'Methods, devices, and systems for dealing with threshold voltage change in memory devices'20118,065,583'Data storage with an outer block code and a stream-based inner code'20118,060,719'Hybrid memory management'20118,051,358'Error recovery storage along a nand-flash string'20118,046,542'Fault-tolerant non-volatile integrated circuit memory'20118,023,334'Program window adjust for memory cell signal line delay'20117,996,727'Error correction for memory'20117,990,763'Memory with weighted multi-page read'20117,990,391'Memory system having multiple address allocation formats and method for use thereof'20117,930,612'Error detection and correction scheme for a memory device'20117,916,148'Memory system and method for improved utilization of read and write bandwidth of a graphics processing system'20117,900,162'Read strobe feedback in a memory system'20117,881,134'Replacing defective columns of memory cells in response to external addresses'20117,861,139'Programming management data for NAND memories'20107,848,142'Fractional bits in memory cells'20107,810,017'Variable sector-count ECC'20107,774,683'Erasure pointer error correction'20107,770,079'Error scanning in flash memory'20107,747,903'Error correction for memory'20107,738,292'Flash memory with multi-bit read'20107,739,576'Variable strength ECC'20107,724,262'Memory system and method for improved utilization of read and write bandwidth of a graphics processing system'20107,512,909'Read strobe feedback in a memory system'20097,453,723'Memory with weighted multi-page read'20087,444,579'Non-systematic coded error correction'20087,397,477'Memory system having multiple address allocation formats and method for use thereof'20087,389,465'Error detection and correction scheme for a memory device'20087,379,068'Memory system and method for improved utilization of read and write bandwidth of a graphics processing system'20087,369,434'Flash memory with multi-bit read'20087,322,002'Erasure pointer error correction'20087,180,522'Apparatus and method for distributed memory control in a graphics processing system'20077,139,182'Cutting CAM peak power by clock regioning'20066,963,343'Apparatus and method for dynamically disabling faulty embedded memory in a graphic processing system'20056,956,577'Embedded memory system and method including data error correction'20056,856,529'Cutting CAM peak power by clock regioning'20056,816,165'Memory system having multiple address allocation formats and method for use thereof'20046,791,555'Apparatus and method for distributed memory control in a graphics processing system'20046,784,889'Memory system and method for improved utilization of read and write bandwidth of a graphics processing system'20046,741,253'Embedded memory system and method including data error correction'20046,734,865'Method and system for mapping various length data regions'20046,646,646'Memory system having programmable multiple and continuous memory regions and method of use thereof'20035,751,699'Multidimensional aspects of an ASIC bus structure'19985,555,540'ASIC bus structure'1996Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1996–1998Based in San Jose, CA, US· patent location history
2003–2021Patents assigned to MICRON TECHNOLOGY INC (166)· patent assignee history
2003–2014Based in San Francisco, CA, US· patent location history
2008–2021Based in Los Gatos, CA, US· patent location history
2011–2015Patents assigned to RADKE WILLIAM H (51)· patent assignee history
2011–2014Patents assigned to FEELEY PETER (20)· patent assignee history
2012–2014Patents assigned to GALBO NEAL A (14)· patent assignee history
2012–2014Patents assigned to TSAI VICTOR Y (14)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 166 | 2003–2021 |
| RADKE WILLIAM Hself | 51 | 2011–2015 |
| FEELEY PETER | 20 | 2011–2014 |
| GALBO NEAL A | 14 | 2012–2014 |
| TSAI VICTOR Y | 14 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Los Gatos, California, US | 154 | 2008–2021 |
| San Francisco, California, US | 33 | 2003–2014 |
| San Jose, California, US | 2 | 1996–1998 |