Inventor
Rahul M. Rao
Inventor
Bangalore, IN
Overview
Patents· 34 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing35%
G01RMeasuring electric variables13%
G11CStatic stores13%
H03KPulse technique13%
B82YSpecific uses or applications of nanostructures4%
C01BNon-metallic elements4%
B01JChemical or physical processes, e.g. catalysis or colloid chemistry2%
B22FWorking metallic powder2%
C01GCompounds containing metals not covered by subclasses c01d or c01f2%
C23CCoating metallic material2%
PatentTitleYear
10,831,620Core pairing in multicore systems202010,354,028Formal verification driven power modeling and design verification201910,216,878Cross-current power modelling using logic simulation201910,195,668Method for continuous and controllable production of single walled carbon nanotubes201910,007,747Cross-current power modelling using logic simulation201810,002,220On the fly netlist compression in power analysis20189,996,649On the fly netlist compression in power analysis20189,934,873Delayed equivalence identification20189,916,406'Cross-current power modelling using logic simulation'20189,754,058'Cross-current power modelling using logic simulation'20179,697,306'Formal verification driven power modeling and design verification'20179,643,847'Method for growth of vertically aligned carbon nanotubes on diamond substrates'20179,519,746'Addressing early mode slack fails by book decomposition'20169,460,251'Formal verification driven power modeling and design verification'20169,280,630'Modified standard cells to address fast paths'20169,064,071'Usage-based temporal degradation estimation for memory elements'20159,058,448'Usage-based temporal degradation estimation for memory elements'20158,966,420'Estimating delay deterioration due to device degradation in integrated circuits'20158,526,219'Enhanced static random access memory stability using asymmetric access transistors and design structure for same'20138,493,774'Performing logic functions on more than one memory cell within an array of memory cells'20138,456,247'Monitoring negative bias temperature instability (NBTI) and/or positive bias temperature instability (PBTI)'20138,139,400'Enhanced static random access memory stability using asymmetric access transistors and design structure for same'20128,004,305'Electronic circuit for measurement of transistor variability and the like'20117,882,370'Static pulsed bus circuit and method having dynamic power supply rail selection'20117,764,080'Methods of operating an electronic circuit for measurement of transistor variability and the like'20107,746,709'Memory circuit with decoupled read and write bit lines and improved write stability'20107,642,864'Circuits and design structures for monitoring NBTI (negative bias temperature instability) effect and/or PBTI (positive bias temperature instability) effect'20107,550,987'Method and circuit for measuring operating and leakage current of individual blocks within an array of test circuit blocks'20097,548,822'Apparatus and method for determining the slew rate of a signal produced by an integrated circuit'20097,495,969'Techniques for improving write stability of memory with decoupled read and write bit lines'20097,439,755'Electronic circuit for measurement of transistor variability and the like'20087,241,479'Thermal CVD synthesis of nanostructures'20077,088,141'Multi-threshold complementary metal-oxide semiconductor (MTCMOS) bus circuit and method for reducing bus power consumption via pulsed standby switching'20066,791,361'Technique for mitigating gate leakage during a sleep state'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2020Patents assigned to IBM (31)· patent assignee history
2004–2006Based in Ann Arbor, MI, US· patent location history
2008–2013Based in Elmsford, NY, US· patent location history
2009–2015Based in Austin, TX, US· patent location history
2012–2015Patents assigned to RAO RAHUL M (7)· patent assignee history
2012–2015Patents assigned to KIM JAE-JOON (6)· patent assignee history
2012–2015Patents assigned to BANSAL ADITYA (5)· patent assignee history
2012–2013Patents assigned to CHUANG CHING-TE K (2)· patent assignee history
2016–2020Based in Bangalore, IN· patent location history
2019Based in Yellow Springs, OH, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 31 | 2004–2020 |
| RAO RAHUL Mself | 7 | 2012–2015 |
| KIM JAE-JOON | 6 | 2012–2015 |
| BANSAL ADITYA | 5 | 2012–2015 |
| CHUANG CHING-TE K | 2 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Bangalore, IN | 13 | 2016–2020 |
| Elmsford, New York, US | 10 | 2008–2013 |
| Austin, Texas, US | 6 | 2009–2015 |
| Ann Arbor, MI, US | 2 | 2004–2006 |
| Yellow Springs, OH, US | 1 | 2019 |