Inventor
PAUL FISCHER
Inventor
US
Overview
Patents· 26 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices28%
H10DInorganic electric semiconductor devices27%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1018%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%
H03HImpedance networks, e.g. resonant circuits5%
G01RMeasuring electric variables1%
H02SGeneration of electric power by conversion of infrared radiation, visible light or ultraviolet light, e.g. using photovoltaic [pv] modules1%
H03JTuning resonant circuits1%
H03KPulse technique1%
H04BTransmission1%
PatentTitleYear
12,375,060Digitally controlled lithographically-defined multi-frequency acoustic resonators202512,080,763Silicide for group III-nitride devices and methods of fabrication202411,948,831Apparatus with multi-wafer based device and method for forming such202411,854,894Integrated circuit device structures and double-sided electrical testing202311,757,027E-D mode 2DEG FET with gate spacer to locally tune VT and improve breakdown202311,715,791Group III-Nitride devices on SOI substrates having a compliant layer202311,705,882Acoustic resonator structure202311,664,417III-N metal-insulator-semiconductor field effect transistors with multiple gate dielectric materials202311,626,513Antenna gate field plate on 2DEG planar FET202311,610,971Cap layer on a polarization layer to preserve channel sheet resistance202311,563,098Transistor gate shape structuring approaches202311,552,075Group III-nitride (III-N) devices and methods of fabrication202311,521,964Schottky diode structures and integration with III-V transistors202211,515,407High breakdown voltage structure for high performance GaN-based HEMT and MOS devices to enable GaN C-MOS202211,489,061Integrated programmable gate radio frequency (RF) switch202211,437,255Epitaxial III-N nanoribbon structures for device fabrication202211,430,873Self aligned gate connected plates for group III-Nitride devices and methods of fabrication202211,404,407Implants to enlarge Schottky diode cross-sectional area for lateral current conduction202211,387,329Tri-gate architecture multi-nanowire confined transistor202211,387,327Silicide for group III-Nitride devices and methods of fabrication202211,380,679FET capacitor circuit architectures for tunable load and input matching202211,362,082Implanted substrate contact for in-process charging control202211,342,232Fabrication of Schottky barrier diode using lateral epitaxial overgrowth202211,335,800Work function based approaches to transistor threshold voltage tuning202211,329,132Transistor with polarization layer superlattice for target threshold voltage tuning202211,158,712Field-effect transistors with buried gates and methods of manufacturing the same2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2025Patents assigned to INTEL CORP (26)· patent assignee history
2021–2025Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 26 | 2021–2025 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 26 | 2021–2025 |