Inventor
Thomas Edward Rosser
Inventor
Austin, TX, US
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing85%
H03KPulse technique8%
H01LSemiconductor devices4%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h104%
PatentTitleYear
9,298,872'Apportioning synthesis effort for better timing closure'20168,638,120'Programmable gate array as drivers for data ports of spare latches'20148,572,536'Spare latch distribution'20138,443,313'Circuit design optimization'20138,386,230'Circuit design optimization'20138,166,439'Techniques for selecting spares to implement a design change in an integrated circuit'20127,979,732'Efficient utilization of a multi-source network of control logic to achieve timing closure in a clocked logic circuit'20117,979,819'Minterm tracing and reporting'20117,552,040'Method and system for modeling logical circuit blocks including transistor gate capacitance loading effects'20097,194,394'Method and apparatus for detecting and correcting inaccuracies in curve-fitted models'20076,922,818'Method of power consumption reduction in clocked circuits'20056,728,944'Method, system, and computer program product for improving wireability near dense clock nets'20046,654,943'Method, system, and computer program product for correcting anticipated problems related to global routing'20036,526,543'Method, system, and computer program product for optimizing logic during synthesis of logic designs'20036,460,166'System and method for restructuring of logic circuitry'20026,339,835'Pseudo-anding in dynamic logic circuits'20026,282,695'System and method for restructuring of logic circuitry'20016,035,110'Identifying candidate nodes for phase assignment in a logic network'20006,018,621'Identifying an optimizable logic region in a logic network'20005,903,467'Selecting phase assignments for candidate nodes in a logic network'19995,774,369'Computer program product for enabling a computer to remove redundancies using quasi algebraic methods'19985,524,082'Redundancy removal using quasi-algebraic methods'1996Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1996–2016Patents assigned to IBM (21)· patent assignee history
1996–1998Based in Poughkeepsie, NY, US· patent location history
1999–2016Based in Austin, TX, US· patent location history
2012–2014Patents assigned to ROSSER THOMAS E (5)· patent assignee history
2013–2014Patents assigned to RANGARAJAN SRIDHAR H (2)· patent assignee history
2013Patents assigned to REICK KEVIN F (2)· patent assignee history
2013Patents assigned to ROBBINS BRYAN J (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 21 | 1996–2016 |
| ROSSER THOMAS Eself | 5 | 2012–2014 |
| RANGARAJAN SRIDHAR H | 2 | 2013–2014 |
| REICK KEVIN F | 2 | 2013 |
| ROBBINS BRYAN J | 2 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 20 | 1999–2016 |
| Poughkeepsie, New York, US | 2 | 1996–1998 |