Inventor
PRITISH NARAYANAN
Inventor
US
Overview
Patents· 23 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Nprimary
G06NComputing arrangements based on specific computational models42%
G11CStatic stores20%
G06FElectric digital data processing18%
H03KPulse technique4%
H03MCoding4%
H04LTransmission of digital information, e.g. telegraphic communication4%
H01LSemiconductor devices2%
H10BElectronic memory devices2%
H10NElectric solid-state devices not otherwise provided for2%
PatentTitleYear
12,596,921Stochastic bitstream generation with in-situ function mapping202612,547,884Hardware implementation of activation functions202612,518,149Implicit vector concatenation within 2D mesh routing202612,456,043Two-dimensional mesh for compute-in-memory accelerator architecture202512,255,656Split pulse width modulation to reduce crossbar array integration time202512,050,997Row-by-row convolutional neural network mapping for analog artificial intelligence network training202412,019,590System, method and article of manufacture for synchronization-free transmittal of neuron values in a hardware artificial neural networks202412,003,240Analog memory-based complex multiply-accumulate (MACC) compute engine202411,977,974Compression of fully connected / recurrent layers of deep network(s) through enforcing spatial locality to weight matrices and effecting frequency compression202411,868,893Efficient tile mapping for row-by-row convolutional neural network mapping for analog artificial intelligence network inference202411,823,740Selective application of multiple pulse durations to crossbar arrays202311,797,833Competitive machine learning accuracy on neuromorphic arrays with non-ideal non-volatile memory devices202311,646,944Configuring computing nodes in a three-dimensional mesh topology202311,580,373System, method and article of manufacture for synchronization-free transmittal of neuron values in a hardware artificial neural networks202311,562,240Efficient tile mapping for row-by-row convolutional neural network mapping for analog artificial intelligence network inference202311,514,981Programming devices and weights in hardware202211,488,664Distributing device array currents across segment mirrors202211,461,640Mitigation of conductance drift in neural network resistive processing units202211,436,479System and method for transfer of analog synaptic weight information onto neuromorphic arrays with non-ideal non-volatile memory device202211,386,320Magnetic domain wall-based non-volatile, linear and bi-directional synaptic weight element202211,347,999Closed loop programming of phase-change memory202211,184,245Configuring computing nodes in a three-dimensional mesh topology202111,182,673Temporal memory adapted for single-shot learning and disambiguation of multiple predictions2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to IBM (22)· patent assignee history
2021–2026Based in US· patent location history
2026Patents assigned to INT BUSINESS MACHINES CORPORATION (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 22 | 2021–2026 |
| INT BUSINESS MACHINES CORPORATION | 1 | 2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 23 | 2021–2026 |