Inventor
Kiyomi Naruke
Inventor
Sagamihara, JP
Overview
Patents· 23 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores30%
H10BElectronic memory devices27%
H10DInorganic electric semiconductor devices27%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests7%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%
G06FElectric digital data processing2%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%
PatentTitleYear
8,873,292'Nonvolatile semiconductor memory device'20148,533,549'Memory system and computer system'20138,319,270'Semiconductor device and method for manufacturing the same'20127,215,576'Nonvolatile semiconductor memory device which erases data in units of one block including a number of memory cells, and data erasing method of the nonvolatile semiconductor memory device'20077,094,652'Semiconductor device and method of manufacturing the same'20066,806,540'Semiconductor device and method of manufacturing the same'20046,376,295'Method for manufacturing a semiconductor memory device with a fine structure'20026,166,958'Semiconductor memory device, method for manufacturing the same, and method for controlling the same'20005,885,872'Method for manufacturing a semiconductor device having an adjustable channel width'19995,838,041'Nonvolatile semiconductor memory device having memory cell transistor provided with offset region acting as a charge carrier injecting region'19985,751,636'Semiconductor memory device having data erasing mechanism'19985,629,548'Semiconductor device with adjustable channel width'19975,623,445'Semiconductor memory device having data erasing mechanism'19975,465,236'Nonvolatile semiconductor memory system with a plurality of erase blocks'19955,452,248'Method of operating a nonvolatile semiconductor memory device'19955,375,094'Nonvolatile semiconductor memory system with a plurality of erase blocks'19945,365,098'Non-volatile semiconductor memory having improved erasure characteristics'19945,243,210'Semiconductor memory device and manufacturing method thereof'19935,208,173'Method of manufacturing non-volatile semiconductor memory device'19935,169,792'Semiconductor device'19925,091,882'Nonvolatile semiconductor memory device and method of operating the same'19925,068,827'Method of applying a program voltage for a non-volatile semiconductor memory and apparatus for implementing the same'19914,675,981'Method of making implanted device regions in a semiconductor using a master mask member'1987Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1987–2014Patents assigned to TOSHIBA KK (23)· patent assignee history
1991–1993Based in Yokohama, JP· patent location history
1994–2013Based in Kanagawa, JP· patent location history
1995–1998Based in Tokyo, JP· patent location history
1997–1999Based in Ebina, JP· patent location history
2000–2014Based in Sagamihara, JP· patent location history
2012–2014Patents assigned to NARUKE KIYOMI (3)· patent assignee history
2012Patents assigned to ARAI FUMITAKA (1)· patent assignee history
2012Patents assigned to MARUYAMA TOHRU (1)· patent assignee history
2013Patents assigned to KONDO SHIGEO (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TOSHIBA KK | 23 | 1987–2014 |
| NARUKE KIYOMIself | 3 | 2012–2014 |
| ARAI FUMITAKA | 1 | 2012 |
| KONDO SHIGEO | 1 | 2013 |
| MARUYAMA TOHRU | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Sagamihara, JP | 7 | 2000–2014 |
| Kanagawa, JP | 4 | 1994–2013 |
| Yokohama, JP | 4 | 1991–1993 |
| Ebina, JP | 3 | 1997–1999 |
| Tokyo, JP | 3 | 1995–1998 |