Inventor
Naohiko Kimizuka
Inventor
Kanagawa, JP
Overview
Patents· 17 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices50%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1025%
H03KPulse technique7%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation7%
H01LSemiconductor devices4%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
PatentTitleYear
9,099,365'Method for manufacturing solid-state imaging device'20158,518,771'Method for manufacturing solid-state imaging device'20137,759,744'Semiconductor device having high dielectric constant layers of different thicknesses'20107,754,570'Semiconductor device'20107,238,996'Semiconductor device'20077,102,183'MOS transistor'20067,033,918'Semiconductor device including p-channel type transistor, and production method for manufacturing such semiconductor device'20067,030,464'Semiconductor device and method of manufacturing the same'20066,969,876'Semiconductor device including p-channel type transistor, and production method for manufacturing such semiconductor device'20056,853,037'Fabrication of low power CMOS device with high reliability'20056,756,635'Semiconductor substrate including multiple nitrided gate insulating films'20046,664,148'Integrated circuit device with switching between active mode and standby mode controlled by digital circuit'20036,388,504'Integrated circuit device with switching between active mode and standby mode controlled by digital circuit'20026,380,594'Semiconductor device'20026,013,577'Method of making an amorphous surface for a gate electrode during the fabrication of a semiconductor device'20006,001,737'Method of forming a semiconductor device having a titanium salicide shallow junction diffusion layer'19995,877,082'Method of manufacturing semiconductor device without plasma damage'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2010Patents assigned to NEC CORP (9)· patent assignee history
1999–2005Based in Tokyo, JP· patent location history
2004–2010Patents assigned to NEC ELECTRONICS CORP (8)· patent assignee history
2005–2015Based in Kanagawa, JP· patent location history
2013–2015Patents assigned to SONY CORP (2)· patent assignee history
2013Patents assigned to KIMIZUKA NAOHIKO (1)· patent assignee history
2013Patents assigned to MATSUMOTO TAKUJI (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| NEC CORP | 9 | 1999–2010 |
| NEC ELECTRONICS CORP | 8 | 2004–2010 |
| SONY CORP | 2 | 2013–2015 |
| KIMIZUKA NAOHIKOself | 1 | 2013 |
| MATSUMOTO TAKUJI | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Kanagawa, JP | 9 | 2005–2015 |
| Tokyo, JP | 8 | 1999–2005 |