Inventor

Roger W. Lindsay

Inventor

Boise, ID, US

Overview

2003–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 45 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Bprimary

H10BElectronic memory devices29%

H01LSemiconductor devices16%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1015%

G11CStatic stores14%

H10DInorganic electric semiconductor devices13%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h109%

H10NElectric solid-state devices not otherwise provided for4%

PatentTitleYear

10,978,474Devices including stack structures, and related methods and electronic systems2021 10,879,259Methods and apparatuses having memory cells including a monolithic semiconductor channel2020 10,833,099Apparatuses and methods for forming multiple decks of memory cells2020 10,658,285Stack of horizontally extending and vertically overlapping features, methods of forming circuitry components, and methods of forming an array of memory cells2020 10,651,315Three dimensional memory2020 10,504,596Apparatuses and methods of forming apparatuses using a partial deck-by-deck process flow2019 10,475,737Stack of horizontally extending and vertically overlapping features, methods of forming circuitry components, and methods of forming an array of memory cells2019 10,446,579Three-dimensional memory devices, and related methods and electronic systems2019 10,340,287Apparatuses and methods for forming multiple decks of memory cells2019 10,319,678Capping poly channel pillars in stacked circuits2019 10,141,330Methods of forming semiconductor device structures, and related semiconductor device structures, semiconductor devices, and electronic systems2018 10,090,317Methods and apparatuses having memory cells including a monolithic semiconductor channel2018 10,079,246Apparatuses and methods for forming multiple decks of memory cells2018 9,929,175'Stack of horizontally extending and vertically overlapping features, methods of forming circuitry components, and methods of forming an array of memory cells'2018 9,853,046Apparatuses and methods for forming multiple decks of memory cells2017 9,564,471'Stack of horizontally extending and vertically overlapping features, methods of forming circuitry components, and methods of forming an array of memory cells'2017 9,437,604'Methods and apparatuses having strings of memory cells including a metal source'2016 9,431,410'Methods and apparatuses having memory cells including a monolithic semiconductor channel'2016 9,425,133'Integrated circuits and methods of forming conductive lines and conductive pads therefor'2016 9,362,300'Apparatuses and methods for forming multiple decks of memory cells'2016 9,318,430'Stack of horizontally extending and vertically overlapping features, methods of forming circuitry components, and methods of forming an array of memory cells'2016 9,263,459'Capping poly channel pillars in stacked circuits'2016 8,945,996'Methods of forming circuitry components and methods of forming an array of memory cells'2015 8,872,252'Multi-tiered semiconductor apparatuses including residual silicide in semiconductor tier'2014 8,803,228'Memory arrays with rows of memory cells coupled to opposite sides of a control gate'2014 8,399,347'Integrated circuits and methods of forming conductive lines and conductive pads therefor'2013 8,369,150'Relaxed metal pitch memory architectures'2013 8,114,737'Methods of forming memory cells on pillars and memories with memory cells on pillars'2012 7,881,113'Relaxed metal pitch memory architectures'2011 7,619,279'Three dimensional flash cell'2009 7,580,279'Flash memory cells with reduced distances between cell elements'2009 7,508,024'Three dimensional flash cell'2009 7,482,630'NAND memory arrays'2009 7,419,895'NAND memory arrays'2008 7,358,561'Source lines for NAND memory devices'2008 7,274,065'Source lines for NAND memory devices'2007 7,208,407'Flash memory cells with reduced distances between cell elements'2007 7,202,129'Source lines for NAND memory devices'2007 7,153,741'Use of selective epitaxial silicon growth in formation of floating gates'2006 7,112,488'Source lines for NAND memory devices'2006 7,019,353'Three dimensional flash cell'2006 6,759,298'Methods of forming an array of flash field effect transistors and circuitry peripheral to such array'2004 6,746,921'Method of forming an array of FLASH field effect transistors and circuitry peripheral to such array'2004 6,645,814'Method of forming an array of FLASH field effect transistors and circuitry peripheral to such array'2003 6,579,763'Methods of forming an array of FLASH field effect transistors and circuitry peripheral to the array'2003

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2003–2021Patents assigned to MICRON TECHNOLOGY INC (43)· patent assignee history

2003–2021Based in Boise, ID, US· patent location history

2012–2019Patents assigned to LINDSAY ROGER W (7)· patent assignee history

2012–2014Patents assigned to JONES LYLE (2)· patent assignee history

2016–2019Patents assigned to INTEL CORP (2)· patent assignee history

2016Patents assigned to BIAN ZAILONG (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MICRON TECHNOLOGY INC	43	2003–2021
LINDSAY ROGER Wself	7	2012–2019
INTEL CORP	2	2016–2019
JONES LYLE	2	2012–2014
BIAN ZAILONG	1	2016

Locations

Location	Patents	Span
Boise, ID, US	45	2003–2021