Inventor

Brett Olsson

Inventor

Cary, NC, US

Overview

65→

Patents

1996–2021

Patent span

Physics

Primary field (CPC G)

Patents· 65 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing98%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%

PatentTitleYear

11,036,519Simultaneously capturing status information for multiple operating modes2021 10,747,537Efficient quantization of compare results2020 10,740,099Instruction to perform a logical operation on conditions and to quantize the boolean result of that operation2020 10,705,841Instruction to perform a logical operation on conditions and to quantize the Boolean result of that operation2020 10,698,688Efficient quantization of compare results2020 10,691,453Vector load with instruction-specified byte count less than a vector size for big and little endian processing2020 10,691,456Vector store instruction having instruction-specified byte count to be stored supporting big and little endian processing2020 10,671,387Vector memory access instructions for big-endian element ordered and little-endian element ordered computer code and data2020 10,620,952Conversion of boolean conditions2020 10,606,588Conversion of Boolean conditions2020 10,540,512Exception preserving parallel data processing of string and unstructured text2020 10,423,412Instructions to count contiguous register elements having a specific value in a selected location2019 10,387,150Instructions to count contiguous register elements having a specific value in a selected location2019 10,346,180Simultaneously capturing status information for multiple operating modes2019 10,318,289Non-faulting compute instructions2019 10,310,854Non-faulting compute instructions2019 10,152,324Virtualization in a bi-endian-mode processor architecture2018 10,120,682Virtualization in a bi-endian-mode processor architecture2018 10,102,007Simultaneously capturing status information for multiple operating modes2018 10,067,716Inaccessibility status indicator2018 10,061,539Inaccessibility status indicator2018 9,785,435'Floating point instruction with selectable comparison attributes'2017 9,727,336'Fine-grained instruction enablement at sub-function granularity based on an indicated subrange of registers'2017 9,727,353'Simultaneously capturing status information for multiple operating modes'2017 9,727,337'Fine-grained instruction enablement at sub-function granularity based on an indicated subrange of registers'2017 9,703,721'Processing page fault exceptions in supervisory software when accessing strings and similar data structures using normal load instructions'2017 9,690,509'Computer instructions for limiting access violation reporting when accessing strings and similar data structures'2017 9,678,886'Processing page fault exceptions in supervisory software when accessing strings and similar data structures using normal load instructions'2017 9,600,282'Endian-mode-independent memory access in a bi-endian-mode processor architecture'2017 9,569,127'Computer instructions for limiting access violation reporting when accessing strings and similar data structures'2017 9,507,595'Execution of multi-byte memory access instruction specifying endian mode that overrides current global endian mode'2016 9,411,585'Multi-addressable register files and format conversions associated therewith'2016 9,395,981'Multi-addressable register files and format conversions associated therewith'2016 8,918,623'Implementing instruction set architectures with non-contiguous register file specifiers'2014 8,893,095'Methods for generating code for an architecture encoding an extended register specification'2014 8,893,079'Methods for generating code for an architecture encoding an extended register specification'2014 8,458,442'Method and structure of using SIMD vector architectures to implement matrix multiplication'2013 8,386,712'Structure for supporting simultaneous storage of trace and standard cache lines'2013 8,312,424'Methods for generating code for an architecture encoding an extended register specification'2012 8,166,281'Implementing instruction set architectures with non-contiguous register file specifiers'2012 7,996,618'Apparatus and method for using branch prediction heuristics for determination of trace formation readiness'2011 7,934,081'Apparatus and method for using branch prediction heuristics for determination of trace formation readiness'2011 7,877,582'Multi-addressable register file'2011 7,849,294'Sharing data in internal and memory representations with dynamic data-driven conversion'2010 7,836,287'Reducing the fetch time of target instructions of a predicted taken branch instruction'2010 7,793,081'Implementing instruction set architectures with non-contiguous register file specifiers'2010 7,644,233'Apparatus and method for supporting simultaneous storage of trace and standard cache lines'2010 7,610,449'Apparatus and method for saving power in a trace cache'2009 7,437,543'Reducing the fetch time of target instructions of a predicted taken branch instruction'2008 7,421,566'Implementing instruction set architectures with non-contiguous register file specifiers'2008 6,343,337'Wide shifting in the vector permute unit'2002 6,334,176'Method and apparatus for generating an alignment control vector'2001 6,327,651'Wide shifting in the vector permute unit'2001 6,298,365'Method and system for bounds comparator'2001 6,282,628'Method and system for a result code for a single-instruction multiple-data predicate compare operation'2001 6,202,141'Method and apparatus for performing vector operation using separate multiplication on odd and even data elements of source vectors'2001 6,202,130'Data processing system for processing vector data and method therefor'2001 5,996,057'Data processing system and method of permutation with replication within a vector register file'1999 5,890,222'Method and system for addressing registers in a data processing unit in an indirect addressing mode'1999 5,887,183'Method and system in a data processing system for loading and storing vectors in a plurality of modes'1999 5,832,533'Method and system for addressing registers in a data processing unit in an indexed addressing mode'1998 5,825,677'Numerically intensive computer accelerator'1998 5,758,176'Method and system for providing a single-instruction, multiple-data execution unit for performing single-instruction, multiple-data operations within a superscalar data processing system'1998 5,680,338'Method and system for vector processing utilizing selected vector elements'1997 5,513,366'Method and system for dynamically reconfiguring a register file in a vector processor'1996

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1996–2021Patents assigned to IBM (64)· patent assignee history

1996–2002Based in Round Rock, TX, US· patent location history

1999–2001Patents assigned to MOTOROLA INC (5)· patent assignee history

1999–2021Based in Cary, NC, US· patent location history

2009–2011Based in Cry, NC, US· patent location history

2012–2017Patents assigned to OLSSON BRETT (9)· patent assignee history

2012–2014Patents assigned to GSCHWIND MICHAEL KARL (6)· patent assignee history

2012–2014Patents assigned to WELLMAN JOHN-DAVID (5)· patent assignee history

2014Based in Research Triangle Park, NC, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	64	1996–2021
OLSSON BRETTself	9	2012–2017
GSCHWIND MICHAEL KARL	6	2012–2014
MOTOROLA INC	5	1999–2001
WELLMAN JOHN-DAVID	5	2012–2014

Locations

Location	Patents	Span
Cary, NC, US	52	1999–2021
Round Rock, Texas, US	9	1996–2002
Cry, NC, US	3	2009–2011
Research Triangle Park, NC, US	1	2014