Inventor
Nick Lindert
Inventor
Beaverton, OR, US
Overview
Patents· 36 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices42%
H10BElectronic memory devices12%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%
H01LSemiconductor devices10%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests8%
H01GCapacitors4%
G11CStatic stores1%
H05KPrinted circuits1%
PatentTitleYear
10,541,143Self-aligned build-up of topographic features202010,109,628Transistor device with gate control layer undercutting the gate dielectric20189,972,541Technique for filling high aspect ratio, narrow structures with multiple metal layers and associated configurations20189,691,839'Metal-insulator-metal (MIM) capacitor with insulator stack having a plurality of metal oxide layers'20179,577,030'Semiconductor structure having a capacitor and metal wiring integrated in a same dielectric layer'20179,565,766'Formation of DRAM capacitor among metal interconnect'20179,224,794'Embedded memory device having MIM capacitor formed in excavated structure'20159,076,758'Rectangular capacitors for dynamic random access (DRAM) and dual-pass lithography methods to form the same'20158,741,720'Penetrating implant for forming a semiconductor device'20148,519,462'6F2 DRAM cell'20138,502,293'Capacitor with recessed plate portion for dynamic random access memory (DRAM) and method to form the same'20138,441,097'Methods to form memory devices having a capacitor with a recessed electrode'20138,441,057'Embedded memory device having MIM capacitor formed in excavated structure'20138,426,927'Penetrating implant for forming a semiconductor device'20138,344,452'Metal gate transistors with raised source and drain regions formed on heavily doped substrate'20138,030,197'Recessed channel array transistor (RCAT) in replacement metal gate (RMG) logic flow'20117,981,756'Common plate capacitor array connections, and processes of making same'20117,951,673'Forming abrupt source drain metal gate transistors'20117,943,468'Penetrating implant for forming a semiconductor device'20117,927,959'Method of patterning a metal on a vertical sidewall of an excavated feature, method of forming an embedded MIM capacitor using same, and embedded memory device produced thereby'20117,781,771'Bulk non-planar transistor having strained enhanced mobility and methods of fabrication'20107,704,833'Method of forming abrupt source drain metal gate transistors'20107,671,358'Plasma implantated impurities in junction region recesses'20107,427,775'Fabricating strained channel epitaxial source/drain transistors'20087,332,439'Metal gate transistors with epitaxial source and drain regions'20087,326,634'Bulk non-planar transistor having strained enhanced mobility and methods of fabrication'20087,314,804'Plasma implantation of impurities in junction region recesses'20087,226,842'Fabricating strained channel epitaxial source/drain transistors'20077,154,118'Bulk non-planar transistor having strained enhanced mobility and methods of fabrication'20067,060,576'Epitaxially deposited source/drain'20067,045,073'Pre-etch implantation damage for the removal of thin film layers'20066,946,350'Controlled faceting of source/drain regions'20056,936,518'Creating shallow junction transistors'20056,808,993'Ultra-thin gate dielectrics'20046,787,440'Method for making a semiconductor device having an ultra-thin high-k gate dielectric'20046,413,802'Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002Based in Berkeley, CA, US· patent location history
2004–2020Patents assigned to INTEL CORP (35)· patent assignee history
2004–2020Based in Beaverton, OR, US· patent location history
2004Based in Hillsboro, OR, US· patent location history
2013–2017Patents assigned to LINDERT NICK (11)· patent assignee history
2013–2014Patents assigned to BOHR MARK T (2)· patent assignee history
2013–2014Patents assigned to CURELLO GIUSEPPE (2)· patent assignee history
2013–2017Patents assigned to GLASSMAN TIMOTHY E (2)· patent assignee history
2013–2018Based in Portland, OR, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 35 | 2004–2020 |
| LINDERT NICKself | 11 | 2013–2017 |
| BOHR MARK T | 2 | 2013–2014 |
| CURELLO GIUSEPPE | 2 | 2013–2014 |
| GLASSMAN TIMOTHY E | 2 | 2013–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Beaverton, OR, US | 31 | 2004–2020 |
| Portland, OR, US | 3 | 2013–2018 |
| Hillsboro, OR, US | 1 | 2004 |
| Berkeley, California, US | 1 | 2002 |