Inventor
Abhishek APPU
Inventor
US
Overview
Patents· 25 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Tprimary
G06TImage data processing or generation, in general33%
G06FElectric digital data processing29%
G06NComputing arrangements based on specific computational models23%
H03MCoding11%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use4%
PatentTitleYear
12,561,276Systems and methods for updating memory side caches in a multi-GPU configuration202612,541,908Apparatus and method for throttling a ray tracing pipeline202612,386,779Dynamic memory reconfiguration202512,306,771Efficient data sharing for graphics data processing operations202512,293,431Sparse optimizations for a matrix accelerator architecture202512,210,477Systems and methods for improving cache efficiency and utilization202512,198,222Architecture for block sparse operations on a systolic array202512,182,035Systems and methods for cache optimization202412,141,094Systolic disaggregation within a matrix accelerator architecture202412,124,383Systems and methods for cache optimization202412,079,155Graphics processor operation scheduling for deterministic latency202412,056,059Systems and methods for cache optimization202412,032,496Efficient data sharing for graphics data processing operations202411,995,029Multi-tile memory management for detecting cross tile access providing multi-tile inference scaling and providing page migration202411,954,062Dynamic memory reconfiguration202411,915,357Apparatus and method for throttling a ray tracing pipeline202411,842,423Dot product operations on sparse matrix elements202311,755,501Efficient data sharing for graphics data processing operations202311,676,239Sparse optimizations for a matrix accelerator architecture202311,631,198Targeted mapping of graphical data for compression202311,620,256Systems and methods for improving cache efficiency and utilization202311,615,584Hierarchical depth buffer back annotation202311,580,361Neural network training mechanism202311,194,722Apparatus and method for improved cache utilization and efficiency on a many core processor202111,175,949Microcontroller-based flexible thread scheduling launching in computing environments2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to INTEL CORP (25)· patent assignee history
2021–2026Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 25 | 2021–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 25 | 2021–2026 |