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Inventor

Tuo-Hung Hou

Inventor
Hsinchu, TW

Overview

15→
Patents
2004–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 15 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H01Lprimary
H01LSemiconductor devices21%
H10DInorganic electric semiconductor devices21%
H10NElectric solid-state devices not otherwise provided for15%
G11CStatic stores13%
H10BElectronic memory devices13%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%
B82YSpecific uses or applications of nanostructures3%
C23CCoating metallic material3%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
PatentTitleYear
10,868,195Impact ionization semiconductor device and manufacturing method thereof202010,510,903Impact ionization semiconductor device and manufacturing method thereof201910,428,427Fabrication method for two-dimensional materials201910,236,061Resistive random access memory having charge trapping layer, manufacturing method thereof, and operation thereof201910,056,432Self-rectifying RRAM cell structure having two resistive switching layers with different bandgaps and RRAM 3D crossbar array architecture20189,978,941Self-rectifying resistive random access memory cell structure20189,715,931'Resistive memory apparatus and a writing method thereof'20179,553,199'FET device having a vertical channel in a 2D material layer'20179,269,434'Resistive memory apparatus and write-in method thereof'20169,059,391'Self-rectifying RRAM cell structure and 3D crossbar array architecture thereof'20158,687,432'Multi-bit resistive-switching memory cell and array'20148,542,540'Nonvolatile memory and methods for manufacturing the same with molecule-engineered tunneling barriers'20137,303,996'High-K gate dielectric stack plasma treatment to adjust threshold voltage characteristics'20077,071,066'Method and structure for forming high-k gates'20066,753,224'Layer of high-k inter-poly dielectric'2004

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2004–2007Patents assigned to TAIWAN SEMICONDUCTOR MFG (3)· patent assignee history
2004–2013Based in Chiayi, TW· patent location history
2013–2014Patents assigned to HOU TUO-HUNG (2)· patent assignee history
2014–2020Based in Hsinchu, TW· patent location history
2015–2019Patents assigned to WINBOND ELECTRONICS CORP (6)· patent assignee history
2017–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (3)· patent assignee history
2017–2019Based in Taichung, TW· patent location history
2019–2020Patents assigned to UNIV NATIONAL CHIAO TUNG (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
WINBOND ELECTRONICS CORP62015–2019
TAIWAN SEMICONDUCTOR MFG32004–2007
TAIWAN SEMICONDUCTOR MFG CO LTD32017–2020
UNIV NATIONAL CHIAO TUNG32019–2020
HOU TUO-HUNGself22013–2014
Locations
LocationPatentsSpan
Hsinchu, TW92014–2020
Chiayi, TW42004–2013
Taichung, TW22017–2019