Inventor
Robert J. Strain
Inventor
San Jose, CA, US
Overview
Patents· 24 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices33%
G11CStatic stores13%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1013%
H03KPulse technique9%
G11BInformation storage based on relative movement between record carrier and transducer7%
H01LSemiconductor devices4%
H10BElectronic memory devices4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
G01HMeasurement of mechanical vibrations or ultrasonic, sonic or infrasonic waves2%
G02BOptical elements, systems or apparatus2%
PatentTitleYear
9,847,404Fluctuation resistant FinFET20179,379,214'Reduced variation MOSFET using a drain-extension-last process'20168,247,840'Apparatus and method for improved leakage current of silicon on insulator transistors using a forward biased diode'20128,048,732'Method for reducing leakage current and increasing drive current in a metal-oxide semiconductor (MOS) transistor'20117,898,297'Method and apparatus for dynamic threshold voltage control of MOS transistors in dynamic logic circuits'20117,863,689'Apparatus for using a well current source to effect a dynamic threshold voltage of a MOS transistor'20117,683,433'Apparatus and method for improving drive-strength and leakage of deep submicron MOS transistors'20107,544,557'Gate defined Schottky diode'20097,485,941'Cobalt silicide schottky diode on isolated well'20096,809,948'Mask programmable read-only memory (ROM) cell'20046,590,797'Multi-bit programmable memory cell having multiple anti-fuse elements'20035,912,779'Method of reading and writing data on a magnetic medium'19995,729,075'Tuneable microelectromechanical system resonator'19985,644,457'Multiple gap read/write head for data storage devices'19975,517,453'Memory with multiple erase modes'19965,453,389'Defect-free bipolar process'19955,426,539'Multiple gap read/write head for data storage devices'19954,728,998'CMOS circuit having a reduced tendency to latch'19884,603,471'Method for making a CMOS circuit having a reduced tendency to latch by controlling the band-gap of source and drain regions'19864,585,299'Process for fabricating optical wave-guiding components and components made by the process'19864,559,696'Ion implantation to increase emitter energy gap in bipolar transistors'19854,480,199'Identification of repaired integrated circuits'19844,347,656'Method of fabricating polysilicon electrodes'19823,935,477'Analog inverter for use in charge transfer apparatus'1976Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1976–1982Patents assigned to BELL TELEPHONE LABOR INC (2)· patent assignee history
1976–1982Based in Plainfield, NJ, US· patent location history
1984–2017Based in San Jose, CA, US· patent location history
1986–1988Patents assigned to FAIRCHILD SEMICONDUCTOR (3)· patent assignee history
1995–1999Patents assigned to NAT SEMICONDUCTOR CORP (5)· patent assignee history
2003–2009Patents assigned to TOWER SEMICONDUCTOR LTD (4)· patent assignee history
2011–2017Patents assigned to SEMI SOLUTIONS LLC (5)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| NAT SEMICONDUCTOR CORP | 5 | 1995–1999 |
| SEMI SOLUTIONS LLC | 5 | 2011–2017 |
| TOWER SEMICONDUCTOR LTD | 4 | 2003–2009 |
| FAIRCHILD SEMICONDUCTOR | 3 | 1986–1988 |
| BELL TELEPHONE LABOR INC | 2 | 1976–1982 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 22 | 1984–2017 |
| Plainfield, New Jersey, US | 2 | 1976–1982 |