Inventor
Anwar Ali
Inventor
San Jose, CA, US
Overview
Patents· 25 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1057%
G06FElectric digital data processing14%
H10DInorganic electric semiconductor devices14%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h109%
G01RMeasuring electric variables6%
PatentTitleYear
8,350,375'Flipchip bump patterns for efficient I-mesh power distribution schemes'20138,151,237'Disabling unused IO resources in platform-based integrated circuits'20128,115,321'Separate probe and bond regions of an integrated circuit'20127,863,716'Method and apparatus of power ring positioning to minimize crosstalk'20117,737,564'Power configuration method for structured ASICs'20107,569,472'Method and apparatus of power ring positioning to minimize crosstalk'20097,554,133'Pad current splitting'20097,430,730'Disabling unused IO resources in platform-based integrated circuits'20087,328,417'Cell-based method for creating slotted metal in semiconductor designs'20087,117,467'Methods for optimizing package and silicon co-design of integrated circuit'20067,107,561'Method of sizing via arrays and interconnects to reduce routing congestion in flip chip integrated circuits'20067,075,179'System for implementing a configurable integrated circuit'20066,998,638'Test structure for detecting bonding-induced cracks'20066,836,026'Integrated circuit design for both input output limited and core limited integrated circuits'20046,815,812'Direct alignment of contacts'20046,798,069'Integrated circuit having adaptable core and input/output regions with multi-layer pad trace conductors'20046,784,102'Laterally interconnecting structures'20046,781,150'Test structure for detecting bonding-induced cracks'20046,781,228'Donut power mesh scheme for flip chip package'20046,768,142'Circuit component placement'20046,704,918'Integrated circuit routing'20046,683,476'Contact ring architecture'20046,671,865'High density input output'20036,657,870'Die power distribution system'20036,591,410'Six-to-one signal/power ratio bump and trace pattern for flip chip design'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2013Patents assigned to LSI LOGIC CORP (18)· patent assignee history
2003–2013Based in San Jose, CA, US· patent location history
2003–2004Based in London, GB· patent location history
2008–2012Patents assigned to LSI CORP (7)· patent assignee history
2012–2013Patents assigned to ALI ANWAR (3)· patent assignee history
2012–2013Patents assigned to DODDAPANENI KALYAN (3)· patent assignee history
2012–2013Patents assigned to LEUNG WILSON (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| LSI LOGIC CORP | 18 | 2003–2013 |
| LSI CORP | 7 | 2008–2012 |
| ALI ANWARself | 3 | 2012–2013 |
| DODDAPANENI KALYAN | 3 | 2012–2013 |
| LEUNG WILSON | 2 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 23 | 2003–2013 |
| London, GB | 2 | 2003–2004 |