Inventor

Chen-Cheng Kuo

Inventor

Jhubei City, TW

Overview

1999–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 83 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1051%

H01LSemiconductor devices27%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices3%

Y10TTechnical subjects covered by former us classification3%

A61CDentistry1%

B05CApparatus for applying fluent materials to surfaces, in general1%

B05DProcesses for applying fluent materials to surfaces, in general1%

B67DDispensing, delivering or transferring liquids, not otherwise provided for1%

H04LTransmission of digital information, e.g. telegraphic communication1%

PatentTitleYear

10,867,811Semiconductor device2020 10,861,710Methods of manufacturing semiconductor devices2020 10,692,848Stress reduction apparatus and method2020 10,692,838Semiconductor packages2020 10,515,917Bump on pad (BOP) bonding structure in semiconductor packaged device2019 10,510,644Package structures and methods for forming the same2019 10,483,225Packaging assembly and method of making the same2019 10,468,366Bonded structures for package and substrate2019 10,304,700Semiconductor device and method2019 10,276,428Semiconductor package and method of fabricating semiconductor package2019 10,163,858Semiconductor packages and manufacturing methods thereof2018 10,163,839Bump on pad (BOP) bonding structure in semiconductor packaged device2018 9,991,218Connector structures of integrated circuits2018 9,905,524'Bump structures in semiconductor device and packaging assembly'2018 9,881,885'Metal routing architecture for integrated circuits'2018 9,786,617'Chip packages and methods of manufacture thereof'2017 9,768,138'Improving the strength of micro-bump joints'2017 9,748,188'Method of forming a bump on pad (BOP) bonding structure in a semiconductor packaged device'2017 9,679,836'Package structures and methods for forming the same'2017 9,673,161'Bonded structures for package and substrate'2017 9,659,903'Method of manufacturing connector structures of integrated circuits'2017 9,472,521'Scheme for connector site spacing and resulting structures'2016 9,397,059'Bonded structures for package and substrate'2016 9,373,598'Connector structures of integrated circuits'2016 9,312,230'Conductive pillar structure for semiconductor substrate and method of manufacture'2016 9,287,191'Semiconductor device package and method'2016 9,257,412'Stress reduction apparatus'2016 9,224,688'Metal routing architecture for integrated circuits'2015 9,219,046'Strength of micro-bump joints'2015 9,196,573'Bump on pad (BOP) bonding structure'2015 9,142,500'Apparatus for lead free solder interconnections for integrated circuits'2015 9,129,818'Semiconductor device having conductive pads and a method of manufacturing the same'2015 9,123,788'Bonded structures for package and substrate'2015 9,093,440'Connector structures of integrated circuits'2015 9,053,989'Elongated bump structure in semiconductor device'2015 9,040,350'Packaging and function tests for package-on-package and system-in-package structures'2015 8,916,971'Multi-direction design for bump pad structures'2014 8,901,736'Strength of micro-bump joints'2014 8,883,628'Electrical connection structure'2014 8,847,387'Robust joint structure for flip-chip bonding'2014 8,829,673'Bonded structures for package and substrate'2014 8,772,950'Methods and apparatus for flip chip substrate with guard rings outside of a die attach region'2014 8,765,497'Packaging and function tests for package-on-package and system-in-package structures'2014 8,753,971'Dummy metal design for packaging structures'2014 8,729,700'Multi-direction design for bump pad structures'2014 8,729,699'Connector structures of integrated circuits'2014 8,716,123'Method of forming an integrated circuit device'2014 8,703,609'Through-substrate via for semiconductor device'2014 8,659,170'Semiconductor device having conductive pads and a method of manufacturing the same'2014 8,659,123'Metal pad structures in dies'2014 8,653,648'Zigzag pattern for TSV copper adhesion'2014 8,604,594'Structures for preventing cross-talk between through-silicon vias and integrated circuits'2013 8,598,030'Process for making conductive post with footing profile'2013 8,546,941'Multi-direction design for bump pad structures'2013 8,476,759'Electrical connection structure'2013 8,476,769'Through-silicon vias and methods for forming the same'2013 8,456,008'Structure and process for the formation of TSVs'2013 8,299,616'T-shaped post for semiconductor devices'2012 8,278,152'Bonding process for CMOS image sensor'2012 8,232,643'Lead free solder interconnections for integrated circuits'2012 8,227,902'Structures for preventing cross-talk between through-silicon vias and integrated circuits'2012 8,227,924'Substrate stand-offs for semiconductor devices'2012 8,202,800'Method of forming through silicon via with dummy structure'2012 8,193,639'Dummy metal design for packaging structures'2012 8,178,970'Strong interconnection post geometry'2012 8,049,327'Through-silicon via with scalloped sidewalls'2011 8,034,708'Structure and process for the formation of TSVs'2011 7,973,413'Through-substrate via for semiconductor device'2011 7,969,013'Through silicon via with dummy structure and method for forming the same'2011 7,919,406'Structure and method for forming pillar bump structure having sidewall protection'2011 7,888,236'Semiconductor device and fabrication methods thereof'2011 7,843,064'Structure and process for the formation of TSVs'2010 7,816,227'Tapered through-silicon via structure'2010 7,785,927'Multi-die wafer level packaging'2010 7,564,115'Tapered through-silicon via structure'2009 7,557,423'Semiconductor structure with a discontinuous material density for reducing eddy currents'2009 7,514,797'Multi-die wafer level packaging'2009 7,179,085'Apparatus for dispensing dental solutions'2007 6,350,680'Pad alignment for AlCu pad for copper process'2002 6,319,821'Dual damascene approach for small geometry dimension'2001 6,183,916'Method for proximity effect compensation on alternative phase-shift masks with bias and optical proximity correction'2001 6,021,921'Liquid dispensing system and method for dispensing'2000 5,869,219'Method for depositing a polyimide film'1999

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1999–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (60)· patent assignee history

1999–2018Based in Hsinchu, TW· patent location history

2001–2020Based in Jhubei City, TW· patent location history

2007Based in Taipei, TW· patent location history

2009Based in Chu Pei, TW· patent location history

2012–2017Patents assigned to KUO CHEN-CHENG (28)· patent assignee history

2012–2017Patents assigned to CHEN CHEN-SHIEN (24)· patent assignee history

2012–2017Patents assigned to CHEN CHIH-HUA (11)· patent assignee history

2016–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (22)· patent assignee history

2018–2020Based in Changhua County, TW· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
TAIWAN SEMICONDUCTOR MFG	60	1999–2016
KUO CHEN-CHENGself	28	2012–2017
CHEN CHEN-SHIEN	24	2012–2017
TAIWAN SEMICONDUCTOR MFG CO LTD	22	2016–2020
CHEN CHIH-HUA	11	2012–2017

Locations

Location	Patents	Span
Jhubei City, TW	71	2001–2020
Hsinchu, TW	7	1999–2018
Changhua County, TW	3	2018–2020
Chu Pei, TW	1	2009
Taipei, TW	1	2007