Inventor
Stephen T. Flannagan
Inventor
Austin, TX, US
Overview
Patents· 42 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores64%
H03KPulse technique24%
G06FElectric digital data processing6%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
H01JElectric discharge tubes or discharge lamps2%
PatentTitleYear
6,473,349'Cascode sense AMP and column select circuit and method of operation'20026,157,583'Integrated circuit memory having a fuse detect circuit and method therefor'20006,044,036'Buffer circuit, memory device, and integrated circuit for receiving digital signals'20006,031,408'Square-law clamping circuit'20005,670,815'Layout for noise reduction on a reference voltage'19975,610,543'Delay locked loop for detecting the phase difference of two signals having different frequencies'19975,485,110'ECL differential multiplexing circuit'19965,477,176'Power-on reset circuit for preventing multiple word line selections during power-up of an integrated circuit memory'19955,440,515'Delay locked loop for detecting the phase difference of two signals having different frequencies'19955,440,514'Write control for a memory using a delay locked loop'19955,426,381'Latching ECL to CMOS input buffer circuit'19955,416,744'Memory having bit line load with automatic bit line precharge and equalization'19955,402,389'Synchronous memory having parallel output data paths'19955,384,737'Pipelined memory having synchronous and asynchronous operating modes'19955,293,081'Driver circuit for output buffers'19945,287,314'BICMOS sense amplifier with reverse bias protection'19945,268,866'Memory with column redundancy and localized column redundancy control signals'19935,256,917'ECL logic gate with voltage protection'19935,184,033'Regulated BiCMOS output buffer'19935,173,877'BICMOS combined bit line load and write gate for a memory'19925,059,829'Logic level shifting circuit with minimal delay'19915,043,602'High speed logic circuit with reduced quiescent current'19914,964,083'Non-address transition detection memory with improved access time'19904,928,268'Memory using distributed data line loading'19904,807,191'Redundancy for a block-architecture memory'19894,807,198'Memory input buffer with hysteresis and dc margin'19894,763,306'Circuit for enabling a transmission gate in response to predecoded signals'19884,763,303'Write-drive data controller'19884,716,302'Identity circuit for an integrated circuit using a fuse and transistor enabled by a power-on reset signal'19874,716,550'High performance output driver'19874,698,788'Memory architecture with sub-arrays'19874,661,931'Asynchronous row and column control'19874,658,381'Bit line precharge on a column address change'19874,644,196'Tri-state differential amplifier'19874,644,197'Reduced power sense amplifier'19874,636,991'Summation of address transition signals'19874,630,239'Chip select speed-up circuit for a memory'19864,547,867'Multiple bit dynamic random-access memory'19854,468,759'Testing method and apparatus for dram'19844,453,237'Multiple bit output dynamic random-access memory'19844,449,207'Byte-wide dynamic RAM with multiplexed internal buses'19844,406,013'Multiple bit output dynamic random-access memory'1983Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1983–1985Patents assigned to INTEL CORP (5)· patent assignee history
1983–1985Based in Beaverton, OR, US· patent location history
1986–2002Patents assigned to MOTOROLA INC (37)· patent assignee history
1986–2002Based in Austin, TX, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MOTOROLA INC | 37 | 1986–2002 |
| INTEL CORP | 5 | 1983–1985 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 37 | 1986–2002 |
| Beaverton, OR, US | 5 | 1983–1985 |