Inventor
Anthony M. Palagonia
Inventor
Underhill, VT, US
Overview
Patents· 32 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1033%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%
G01RMeasuring electric variables13%
B24BMachines, devices, or processes for grinding or polishing8%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests7%
Y10TTechnical subjects covered by former us classification5%
C09KMaterials for miscellaneous applications, not provided for elsewhere3%
H10DInorganic electric semiconductor devices3%
B82YSpecific uses or applications of nanostructures2%
E04FFinishing work on buildings, e.g. stairs, floors2%
PatentTitleYear
6,574,925'Emergency stairwell for multistory buildings'20036,425,092'Method and apparatus for preventing thermal failure in a semiconductor device through redundancy'20026,400,166'Micro probe and method of fabricating same'20026,333,546'Micro fusible link for semiconductor devices and method of manufacture'20016,294,453'Micro fusible link for semiconductor devices and method of manufacture'20016,242,778'Cooling method for silicon on insulator devices'20016,239,469'Method for fabrication of silicon on insulator substrates'20016,232,143'Micro probe ring assembly and method of fabrication'20016,194,253'Method for fabrication of silicon on insulator substrates'20016,188,231'Method for forming an interposer for making temporary contact with pads of a semiconductor chip'20016,171,436'Apparatus for removing slurry particles'20016,160,302'Laser fusible link'20006,059,982'Micro probe assembly and method of fabrication'20006,050,326'Method and apparatus for cooling an electronic device'20006,037,786'Testing integrated circuit chips'20006,037,661'Multichip module'20006,014,032'Micro probe ring assembly and method of fabrication'20005,944,588'Chemical mechanical polisher'19995,934,977'Method of planarizing a workpiece'19995,925,924'Methods for precise definition of integrated circuit chip edges'19995,907,785'Wafer with elevated contact substructures'19995,896,870'Method of removing slurry particles'19995,895,978'High density signal multiplexing interposer'19995,874,782'Wafer with elevated contact structures'19995,872,025'Method for stacked three dimensional device manufacture'19995,785,584'Planarizing apparatus with deflectable polishing pad'19985,751,057'Lead on chip lead frame design without jumpover wiring'19985,691,248'Methods for precise definition of integrated circuit chip edges'19975,679,609'Fabrication, testing and repair of multichip semiconductor structures having connect assemblies with fuses'19975,661,330'Fabrication, testing and repair of multichip semiconductor structures having connect assemblies with fuses'19975,651,857'Sidewall spacer using an overhang'19975,604,377'Semiconductor chip high density packaging'1997Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1997–2002Patents assigned to IBM (31)· patent assignee history
1997–2003Based in Underhill, VT, US· patent location history
1997Based in Undorhill, VT, US· patent location history
2003Patents assigned to MAXIMUS TECHNOLOGIES (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 31 | 1997–2002 |
| MAXIMUS TECHNOLOGIES | 1 | 2003 |
Locations
| Location | Patents | Span |
|---|---|---|
| Underhill, VT, US | 31 | 1997–2003 |
| Undorhill, VT, US | 1 | 1997 |