Inventor
Yukio Morozumi
Inventor
Chino, JP
Overview
Patents· 20 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1044%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1027%
Y10TTechnical subjects covered by former us classification10%
H10DInorganic electric semiconductor devices5%
G04FTime-interval measuring2%
H01GCapacitors2%
H01MProcesses or means, e.g. batteries, for the direct conversion of chemical energy into electrical energy2%
H01RElectrically-conductive connections2%
Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution2%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
PatentTitleYear
10,804,521Battery terminal20207,091,609'Semiconductor devices including an alloy layer and a wetting layer on an interlayer dielectric'20066,812,123'Semiconductor devices and methods for manufacturing the same'20046,723,628'Method for forming bonding pad structures in semiconductor devices'20046,710,460'Semiconductor devices and methods for manufacturing the same'20046,664,644'Semiconductor device and method for manufacturing the same'20036,569,785'Semiconductor integrated circuit device having internal tensile and internal compression stress'20036,559,545'Semiconductor devices and methods for manufacturing semiconductor devices'20036,498,090'Semiconductor devices and methods for manufacturing the same'20026,399,477'Semiconductor devices and methods for manufacturing semiconductor devices'20026,358,830'Method for manufacturing semiconductor device having interlayer dielectric film layers with like etch speeds'20026,246,105'Semiconductor device and manufacturing process thereof'20016,194,304'Semiconductor device and method of fabricating the same'20016,137,176'Semiconductor device and method of fabricating the same'20005,514,624'Method of manufacturing a microelectronic interlayer dielectric structure'19965,376,435'Microelectronic interlayer dielectric structure'19945,266,525'Microelectronic interlayer dielectric structure and methods of manufacturing same'19935,051,807'Integrated semiconductor structure with incorporated alignment markings'19914,068,285'Variable capacitor'19783,988,181'METHOD OF DOPING A POLYCRYSTALLINE SILICON LAYER'1976Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1976Patents assigned to IMAI FUKASHI (1)· patent assignee history
1976Patents assigned to MOROZUMI YUKIO (1)· patent assignee history
1976–2003Based in Nagano, JP· patent location history
1978Patents assigned to SUWA SEIKOSHA KK (1)· patent assignee history
1978–2006Based in Chino, JP· patent location history
1991–2006Patents assigned to SEIKO EPSON CORP (17)· patent assignee history
1993–1996Based in Suwa, JP· patent location history
2020Patents assigned to AOYAMA SEISAKUSHO (1)· patent assignee history
2020Based in Toyota, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SEIKO EPSON CORP | 17 | 1991–2006 |
| AOYAMA SEISAKUSHO | 1 | 2020 |
| IMAI FUKASHI | 1 | 1976 |
| MOROZUMI YUKIOself | 1 | 1976 |
| SUWA SEIKOSHA KK | 1 | 1978 |
Locations
| Location | Patents | Span |
|---|---|---|
| Chino, JP | 13 | 1978–2006 |
| Nagano, JP | 3 | 1976–2003 |
| Suwa, JP | 3 | 1993–1996 |
| Toyota, JP | 1 | 2020 |