Inventor
Jehoshua Bruck
Inventor
La Canada, CA, US
Overview
Patents· 49 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing29%
H03MCoding21%
H04LTransmission of digital information, e.g. telegraphic communication17%
G11CStatic stores16%
H04QSelecting7%
H04JMultiplex communication4%
H04WWireless communication networks2%
G11BInformation storage based on relative movement between record carrier and transducer1%
H04HBroadcast communication1%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%
PatentTitleYear
10,665,310Error characterization and mitigation for 16nm MLC NAND flash memory under total ionizing dose effect202010,437,525Communication efficient secret sharing201910,430,272Secure raid schemes for distributed storage201910,379,945Asymmetric error correction and flash-memory rewriting using polar codes201910,224,111Error characterization and mitigation for 16 nm MLC NAND flash memory under total ionizing dose effect201910,191,803Rewriting flash memories by message passing20199,983,808NAND flash reliability with rank modulation20189,946,475Joint rewriting and error correction in write-once memories20189,916,197'Rank-modulation rewriting codes for flash memories'20189,870,834'Error characterization and mitigation for 16nm MLC NAND flash memory under total ionizing dose effect'20189,666,280'Flash memories using minimum push up, multi-cell and multi-permutation schemes for data storage'20179,230,652'Flash memories using minimum push up, multi-cell and multi-permutation schemes for data storage'20169,086,955'Rank-modulation rewriting codes for flash memories'20158,694,866'MDS array codes with optimal building'20148,296,623'Codes for limited magnitude asymmetric errors in flash memories'20128,245,094'Rank modulation for flash memories'20128,225,180'Error correcting codes for rank modulation'20127,752,332'Geometric routing in wireless networks'20107,680,147'Data transmission system and method'20107,656,706'Storing information in a memory'20107,613,827'Distributed traffic controller for network data'20097,546,354'Dynamic network based storage with high availability'20097,443,319'Precision-resolution constrained coding scheme'20087,299,294'Distributed traffic controller for network data'20077,249,341'Synthesis of cyclic combinational circuits'20077,129,863'Interval modulation coding'20066,801,949'Distributed server cluster with graphical user interface'20046,691,165'Distributed server cluster for controlling network traffic'20046,279,128'Autonomous system for recognition of patterns formed by stored data during computer memory scrubbing'20016,226,683'Increasing probability multi-stage network'20016,034,956'Method of simultaneously attempting parallel path connections in a multi-stage interconnection network'20005,890,151'Method and system for performing partial-sum queries on a data cube'19995,835,024'Multi-stage interconnection network with selectable function switching apparatus'19985,778,011'Method and apparatus for writing and protecting against random and cluster errors in image blocks'19985,774,067'Flash-flooding multi-stage interconnection network with parallel path seeking switching elements'19985,734,826'Variable cyclic redundancy coding method and apparatus for use in a multistage network'19985,579,475'Method and means for encoding and rebuilding the data contents of up to two unavailable DASDS in a DASD array using simple non-recursive diagonal and row parity'19965,561,805'System for selectively packing together datablocks and efficiently routing independent of network topology in a parallel computer system in accordance with a selected numbering system'19965,542,048'Increasing probability multi-stage network'19965,513,313'Method for generating hierarchical fault-tolerant mesh architectures'19965,461,631'Method for bit resynchronization of code-constrained sequences'19955,386,420'Coding method for correction and detection of skewed transitions in parallel asynchronous communication systems'19955,357,528'Depth-2 threshold logic circuits for logic and arithmetic functions'19945,345,229'Adaptive switching apparatus for multi-stage networks'19945,285,454'Method and apparatus for encoding and decoding unordered error correcting codes'19945,280,485'Coding method for skewed transition detection in parallel asynchronous communication system'19945,280,607'Method and apparatus for tolerating faults in mesh architectures'19945,280,533'Coding method for skewed transition correction in parallel asynchronous communication systems'19945,271,014'Method and apparatus for a fault-tolerant mesh with spare nodes'1993Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1993–2001Patents assigned to IBM (21)· patent assignee history
1993–2001Based in Palo Alto, CA, US· patent location history
1998–2019Based in La Canada, CA, US· patent location history
2004–2019Based in Pasadena, CA, US· patent location history
2006–2020Patents assigned to CALIFORNIA INST OF TECHN (23)· patent assignee history
2010–2019Patents assigned to TEXAS A & M UNIV SYS (5)· patent assignee history
2012–2014Patents assigned to BRUCK JEHOSHUA (4)· patent assignee history
2017–2018Patents assigned to TEXAS A&M UNIV SYSTEM (4)· patent assignee history
2019–2020Based in La Canada Flintridge, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| CALIFORNIA INST OF TECHN | 23 | 2006–2020 |
| IBM | 21 | 1993–2001 |
| TEXAS A & M UNIV SYS | 5 | 2010–2019 |
| BRUCK JEHOSHUAself | 4 | 2012–2014 |
| TEXAS A&M UNIV SYSTEM | 4 | 2017–2018 |
Locations
| Location | Patents | Span |
|---|---|---|
| La Canada, California, US | 23 | 1998–2019 |
| Palo Alto, California, US | 15 | 1993–2001 |
| Pasadena, California, US | 9 | 2004–2019 |
| La Canada Flintridge, California, US | 2 | 2019–2020 |