Inventor

Jerome M. Eldridge

Inventor

Los Gatos, CA, US

Overview

1980–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 83 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices19%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1014%

H10BElectronic memory devices12%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%

G11CStatic stores10%

B81BMicrostructural devices or systems, e.g. micromechanical devices5%

Y10TTechnical subjects covered by former us classification5%

B23KSoldering or unsoldering4%

B41JTypewriters3%

F03GSpring, weight, inertia or like motors3%

PatentTitleYear

11,002,569Actuator control system utilizing circuit card assembly2021 10,998,116VDT with high permeability shield2021 9,147,735'Apparatus and method for controlling diffusion'2015 7,727,868'Apparatus and method for controlling diffusion'2010 7,626,252'Multi-chip electronic package and cooling system'2009 7,592,242'Apparatus and method for controlling diffusion'2009 7,585,753'Controlling diffusion in doped semiconductor regions'2009 7,545,674'Flash memory with low tunnel barrier interpoly insulators'2009 7,508,025'Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators'2009 7,504,687'Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators'2009 7,476,925'Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interploy insulators'2009 7,473,956'Atomic layer deposition of metal oxide and/or low assymmetrical tunnel barrier interpoly insulators'2009 7,465,983'Low tunnel barrier insulators'2008 7,446,368'Deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators'2008 7,391,072'Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers'2008 7,372,097'Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers'2008 7,372,096'Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers'2008 7,347,349'Apparatus and method for printing micro metal structures'2008 7,322,511'Apparatus and method for printing micro metal structures'2008 7,301,221'Controlling diffusion in doped semiconductor regions'2007 7,297,617'Method for controlling diffusion in semiconductor regions'2007 7,192,827'Methods of forming capacitor structures'2007 7,175,772'Small scale actuators and methods for their formation and use'2007 7,168,163'Full wafer silicon probe card for burn-in and testing and test system including same'2007 7,166,883'Capacitor structures'2007 7,135,734'Graded composition metal oxide tunnel barrier interpoly insulators'2006 7,136,302'Integrated circuit memory device and method'2006 7,132,711'Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers'2006 7,126,183'Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers'2006 7,115,493'Antifuse structures, methods, and applications'2006 7,112,841'Graded composition metal oxide tunnel barrier interpoly insulators'2006 7,068,544'Flash memory with low tunnel barrier interpoly insulators'2006 7,067,421'Multilevel copper interconnect with double passivation'2006 7,042,043'Programmable array logic or memory devices with asymmetrical tunnel barriers'2006 7,028,879'System for depositing connection sites on micro C-4 semiconductor die'2006 7,027,328'Integrated circuit memory device and method'2006 6,975,027'Multi-chip electronic package and cooling system'2005 6,958,287'Micro C-4 semiconductor die'2005 6,955,968'Graded composition gate insulators to reduce tunneling barriers in flash memory devices'2005 6,953,706'Method of providing a semiconductor package having an internal heat-activated hydrogen source'2005 6,952,032'Programmable array logic or memory devices with asymmetrical tunnel barriers'2005 6,935,355'Small scale actuators and methods for their formation and use'2005 6,912,778'Methods of fabricating full-wafer silicon probe cards for burn-in and testing of semiconductor devices'2005 6,908,827'Perovskite-type material forming methods, capacitor dielectric forming methods, and capacitor constructions'2005 6,909,171'Microelectronic device package filled with liquid or pressurized gas and associated method of manufacture'2005 6,902,984'Methods of forming void regions, dielectric regions and capacitor constructions'2005 6,897,513'Perovskite-type material forming methods, capacitor dielectric forming methods, and capacitor constructions'2005 6,888,232'Semiconductor package having a heat-activated source of releasable hydrogen'2005 6,878,396'Micro C-4 semiconductor die and method for depositing connection sites thereon'2005 6,861,287'Multiple chip stack structure and cooling system'2005 6,861,727'Antifuse structures, methods, and applications'2005 6,834,663'Small scale actuators and methods for their formation and use'2004 6,794,261'Methods of forming void regions, dielectric regions and capacitor constructions'2004 6,778,441'Integrated circuit memory device and method'2004 6,747,347'Multi-chip electronic package and cooling system'2004 6,730,575'Methods of forming perovskite-type material and capacitor dielectric having perovskite-type crystalline structure'2004 6,709,968'Microelectronic device with package with conductive elements and associated method of manufacture'2004 6,686,654'Multiple chip stack structure and cooling system'2004 6,672,325'Small scale actuators and methods for their formation and use'2004 6,674,167'Multilevel copper interconnect with double passivation'2004 6,670,719'Microelectronic device package filled with liquid or pressurized gas and associated method of manufacture'2003 6,667,219'Methods for forming void regions, dielectric regions and capacitor constructions'2003 6,639,267'Capacitor dielectric having perovskite-type crystalline structure'2003 6,614,092'Microelectronic device package with conductive elements and associated method of manufacture'2003 6,586,797'Graded composition gate insulators to reduce tunneling barriers in flash memory devices'2003 6,561,479'Small scale actuators and methods for their formation and use'2003 6,491,969'Print head for ejecting liquid droplets and associated methods'2002 6,461,931'Thin dielectric films for DRAM storage capacitors'2002 6,458,687'Method for forming conductive structures'2002 6,435,396'Print head for ejecting liquid droplets'2002 6,288,437'Antifuse structures methods and applications'2001 6,140,200'Methods of forming void regions dielectric regions and capacitor constructions'2000 6,121,131'Method for forming conductive structures'2000 5,275,695'Process for generating beveled edges'1994 5,059,989'Thermal edge jet drop-on-demand ink jet print head'1991 4,870,433'Thermal drop-on-demand ink jet print head'1989 4,847,636'Thermal drop-on-demand ink jet print head'1989 4,792,818'Thermal drop-on-demand ink jet print head'1988 4,791,440'Thermal drop-on-demand ink jet print head'1988 4,561,040'Cooling system for VLSI circuit chips'1985 4,521,451'Encapsulated magnetic recording disk'1985 4,368,220'Passivation of RIE patterned al-based alloy films by etching to remove contaminants and surface oxide followed by oxidation'1983 4,183,781'Stabilization process for aluminum microcircuits which have been reactive-ion etched'1980

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1980–1994Patents assigned to IBM (9)· patent assignee history

1980–1985Based in Saratoga, CA, US· patent location history

1985–2015Based in Los Gatos, CA, US· patent location history

2000–2015Patents assigned to MICRON TECHNOLOGY INC (71)· patent assignee history

2015Patents assigned to ELDRIDGE JEROME M (1)· patent assignee history

2015Patents assigned to FARRAR PAUL A (1)· patent assignee history

2021Patents assigned to HAMILTON SUNDSTRAND CORP (2)· patent assignee history

2021Based in Ellington, CT, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MICRON TECHNOLOGY INC	71	2000–2015
IBM	9	1980–1994
HAMILTON SUNDSTRAND CORP	2	2021
ELDRIDGE JEROME Mself	1	2015
FARRAR PAUL A	1	2015

Locations

Location	Patents	Span
Los Gatos, California, US	78	1985–2015
Saratoga, California, US	3	1980–1985
Ellington, CT, US	2	2021