Inventor
Kazumasa Nawata
Inventor
Kawasaki, JP
Overview
Patents· 8 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Kprimary
H03KPulse technique40%
H10DInorganic electric semiconductor devices20%
G05FSystems for regulating electric or magnetic variables13%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests7%
PatentTitleYear
5,216,296'Logic circuit having sharper falling edge transition'19935,144,158'ECL latch circuit having a noise resistance circuit in only one feedback path'19924,918,563'ECL gate array semiconductor device with protective elements'19904,866,303'ECL gate array with collector resistance compensation for distance from power supply pad'19894,678,935'Inner bias circuit for generating ECL bias voltages from a single common bias voltage reference'19874,599,521'Bias circuit with voltage and temperature compensation for an emitter coupled logic circuit'19864,375,999'Method of manufacturing a semiconductor device'19834,278,897'Large scale semiconductor integrated circuit device'1981Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1981–1993Patents assigned to FUJITSU LTD (7)· patent assignee history
1981–1993Based in Kawasaki, JP· patent location history
1983Patents assigned to VLSI TECHNOLOGY RES ASS (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| FUJITSU LTD | 7 | 1981–1993 |
| VLSI TECHNOLOGY RES ASS | 1 | 1983 |
Locations
| Location | Patents | Span |
|---|---|---|
| Kawasaki, JP | 8 | 1981–1993 |