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Inventor

Rafael C. Camarota

Inventor
San Jose, CA, US

Overview

55→
Patents
1990–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 55 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H03Kprimary
H03KPulse technique39%
G11CStatic stores13%
G06FElectric digital data processing12%
G01RMeasuring electric variables9%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%
H01LSemiconductor devices7%
H10DInorganic electric semiconductor devices3%
G06KGraphical data reading2%
H03MCoding2%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h102%
PatentTitleYear
10,963,411Integrating rows of input/output blocks with memory controllers in a columnar programmable fabric archeture202110,929,331Layered boundary interconnect202110,784,121Standalone interface for stacked silicon interconnect (SSI) technology integration202010,763,862Boundary logic interface202010,673,440Unified programmable computational memory and configuration network202010,621,132Auto address generation for switch network202010,502,785Test network for a network on a chip and a configuration network201910,177,107Heterogeneous ball pattern package201910,069,497Circuit for and method of implementing a scan chain in programmable resources of an integrated circuit20189,911,465'High bandwidth memory (HBM) bandwidth aggregation switch'20189,882,562'Rotated integrated circuit die and chip packages having the same'20189,547,034'Monolithic integrated circuit die having modular die regions stitched together'20179,204,542'Multi-use package substrate'20159,083,340'Memory matrix'20159,026,872'Flexible sized die for use in multi-die integrated circuit'20158,913,455'Dual port memory cell'20148,869,088'Oversized interposer formed from a multi-pattern region mask'20148,712,718'Predicting performance of an integrated circuit'20148,539,420'Method and apparatus for self-annealing multi-die interconnect redundancy control'20138,502,676'PLD package with coordinated RFID tag'20138,330,741'Multi-touch decoder for digital resistive screen overlay'20128,086,922'Programmable logic device with differential communications support'20118,081,079'PLD package with coordinated RFID TAG'20117,958,416'Programmable logic device with differential communications support'20117,733,159'High voltage tolerance emulation using voltage clamp for oxide stress protection'20107,550,994'Programmable logic device with on-chip nonvolatile user memory'20097,550,995'Method and system for using boundary scan in a programmable logic device'20097,505,331'Programmable logic device with differential communications support'20097,486,106'CPLD for multi-wire keyboard decode with timed power control circuit'20097,276,935'Input buffer with selectable threshold and hysteresis option'20077,248,070'Method and system for using boundary scan in a programmable logic device'20077,242,218'Techniques for combining volatile and non-volatile programmable logic on an integrated circuit'20077,190,190'Programmable logic device with on-chip nonvolatile user memory'20077,154,297'Programmable logic with programmable volatility'20067,023,238'Input buffer with selectable threshold and hysteresis option'20066,744,274'Programmable logic core adapter'20046,462,576'Programmable logic device'20026,418,045'Efficient and robust random access memory cell suitable for programmable logic configuration control'20026,294,925'Programmable logic device'20016,292,388'Efficient and robust random access memory cell suitable for programmable logic configuration control'20016,278,311'Method for minimizing instantaneous currents when driving bus signals'20016,255,847'Programmable logic device'20016,229,336'Programmable integrated circuit device with slew control and skew control'20016,066,977'Programmable output voltage levels'20005,805,503'Non-disruptive randomly addressable memory system'19985,488,582'Non-disruptive, randomly addressable memory system'19965,341,040'High performance output buffer with reduced ground bounce'19945,336,950'Configuration features in a configurable logic array'19945,319,255'Power up detect circuit for configurable logic array'19945,317,209'Dynamic three-state bussing capability in a configurable logic array'19945,298,805'Versatile and efficient cell-to-local bus interface in a configurable logic array'19945,245,227'Versatile programmable logic cell for use in configurable logic arrays'19935,218,240'Programmable logic cell and array with bus repeaters'19935,144,166'Programmable logic cell and array'19924,910,712'Memory cell with a plurality of pass gates'1990

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1990–2021Based in San Jose, CA, US· patent location history
1994Patents assigned to NAT SEMICONDUCTOR CORP (5)· patent assignee history
2000–2002Patents assigned to LATTICE SEMICONDUCTOR CORP (6)· patent assignee history
2000–2011Based in Sunnyvale, CA, US· patent location history
2006–2013Patents assigned to ALTERA CORP (16)· patent assignee history
2011–2013Based in Los Gatos, CA, US· patent location history
2013–2021Patents assigned to XILINX INC (19)· patent assignee history
2013–2015Patents assigned to CAMAROTA RAFAEL C (4)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
XILINX INC192013–2021
ALTERA CORP162006–2013
LATTICE SEMICONDUCTOR CORP62000–2002
NAT SEMICONDUCTOR CORP51994
CAMAROTA RAFAEL Cself42013–2015
Locations
LocationPatentsSpan
San Jose, California, US301990–2021
Sunnyvale, California, US222000–2011
Los Gatos, California, US32011–2013