Inventor
William A. Hughes
Inventor
San Jose, CA, US
Overview
Patents· 60 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing72%
H04LTransmission of digital information, e.g. telegraphic communication12%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use11%
G01RMeasuring electric variables1%
G11CStatic stores1%
H03MCoding1%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%
PatentTitleYear
9,355,034'Removal and optimization of coherence acknowledgement responses in an interconnect'20168,996,816'Method and apparatus for selectively bypassing a cache for trace collection in a processor'20158,954,635'Buffer management using freelist buffers'20158,787,368'Crossbar switch with primary and secondary pickers'20148,756,442'System for processor power limit management'20148,732,410'Method and apparatus for accelerated shared data migration'20148,606,999'Cache partitioning'20138,595,563'Method and circuitry for debugging a power-gated circuit'2013RE044487'Command packet packing to mitigate CRC overhead'20138,504,854'Managing multiple operating points for stable virtual frequencies'20138,195,887'Processor power management and method'20127,996,653'Shared resources in a chip multiprocessor'20117,882,327'Communicating between partitions in a statically partitioned multiprocessing system'20117,881,303'Command packet packing to mitigate CRC overhead'20117,877,558'Memory controller prioritization scheme'20117,844,758'Dynamic resource allocation scheme for efficient use of a queue'20107,840,873'Partial CRC insertion in data packets for early forwarding'20107,840,780'Shared resources in a chip multiprocessor'20107,707,341'Virtualizing an interrupt controller'20107,603,550'Computer system including a secure execution mode-capable CPU and a security services processor connected via a secure communication path'20097,603,551'Initialization of a computer system including a secure execution mode-capable processor'20097,480,784'Ensuring deadlock free operation for peer to peer traffic in an input/output memory management unit (IOMMU)'20097,383,423'Shared resources in a chip multiprocessor'20087,328,371'Core redundancy in a chip multiprocessor for highly reliable systems'20087,295,563'Method and apparatus for routing packets that have ordering requirements'20077,296,167'Combined system responses in a chip multiprocessor'20077,274,692'Method and apparatus for routing packets that have multiple destinations'20077,263,457'System and method for operating components of an integrated circuit at independent frequencies and/or voltages'20077,221,678'Method and apparatus for routing packets'20077,210,009'Computer system employing a trusted execution environment including a memory controller configured to clear memory'20077,174,467'Message based power management in a multi-processor system'20077,165,132'Processing node including a plurality of processor cores and an interconnect configurable in a test-mode to cause first and second transaction source indicators to be interchanged'20077,155,572'Method and apparatus for injecting write data into a cache'20067,146,510'Use of a signal line to adjust width and/or frequency of a communication link during system operation'20067,146,477'Mechanism for selectively blocking peripheral device accesses to system memory'20067,107,367'Method for efficient buffer tag allocation'20067,073,133'Objects and methods for accessing a data source and enhancing an application'20067,058,791'Establishing a mode indication responsive to two or more indications'20067,051,218'Message based power management'20067,043,679'Piggybacking of ECC corrections behind loads'20067,009,618'Integrated I/O Remapping mechanism'20066,973,543'Partial directory cache for reducing probe traffic in multiprocessor systems'20056,934,903'Using microcode to correct ECC errors in a processor'20056,757,793'Reducing probe traffic in multiprocessor systems using a victim record table'20046,718,444'Read-modify-write for partial writes in a memory controller'20046,715,055'Apparatus and method for allocating buffer space'20046,665,788'Reducing latency for a relocation cache lookup and address mapping in a distributed memory system'20036,662,280'Store buffer which forwards data based on index and optional way match'20036,571,318'Stride based prefetcher with confidence counter and dynamic prefetch-ahead mechanism'20036,549,990'Store to load forwarding using a dependency link file'20036,473,832'Load/store unit having pre-cache and post-cache queues for low latency load memory operations'20026,473,837'Snoop resynchronization mechanism to preserve read ordering'20026,473,849'Implementing locks in a distributed processing system'20026,446,189'Computer system including a novel address translation mechanism'20026,427,193'Deadlock avoidance using exponential backoff'20026,415,360'Minimizing self-modifying code checks for uncacheable memory types'20026,393,536'Load/store unit employing last-in-buffer indication for rapid load-hit-store'20026,370,600'Staging buffer for translating clock domains when source clock frequency exceeds target clock frequency'20026,266,744'Store to load forwarding using a dependency link file'20015,813,035'Microprocessor employing a technique for restoration of an aborted cycle following a snoop writeback operation'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2015Patents assigned to ADVANCED MICRO DEVICES INC (52)· patent assignee history
1998Based in Austin, TX, US· patent location history
2001–2009Based in Burlingame, CA, US· patent location history
2002Based in Sunnyvale, CA, US· patent location history
2006–2016Based in San Jose, CA, US· patent location history
2006Based in Randolph, NJ, US· patent location history
2010–2013Patents assigned to GLOBALFOUNDRIES INC (6)· patent assignee history
2012–2015Patents assigned to HUGHES WILLIAM A (8)· patent assignee history
2013–2015Patents assigned to DONLEY GREGGORY D (4)· patent assignee history
2013–2015Patents assigned to FERTIG MICHAEL K (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADVANCED MICRO DEVICES INC | 52 | 1998–2015 |
| HUGHES WILLIAM Aself | 8 | 2012–2015 |
| GLOBALFOUNDRIES INC | 6 | 2010–2013 |
| DONLEY GREGGORY D | 4 | 2013–2015 |
| FERTIG MICHAEL K | 3 | 2013–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 30 | 2006–2016 |
| Burlingame, California, US | 27 | 2001–2009 |
| Randolph, New Jersey, US | 1 | 2006 |
| Sunnyvale, California, US | 1 | 2002 |
| Austin, Texas, US | 1 | 1998 |