Inventor
Jeffrey A. Zitz
Inventor
Poughkeepsie, NY, US
Overview
Patents· 57 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1039%
H01LSemiconductor devices20%
H05KPrinted circuits15%
Y10TTechnical subjects covered by former us classification7%
G06FElectric digital data processing5%
H10NElectric solid-state devices not otherwise provided for4%
G01NInvestigating or analysing materials by determining their chemical or physical properties2%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h102%
G01LMeasuring force, stress, torque, work, mechanical power, mechanical efficiency, or fluid pressure2%
C08LCompositions of macromolecular compounds1%
PatentTitleYear
10,978,314Multi integrated circuit chip carrier package202110,905,029Cooling structure for electronic boards202110,892,170Fabricating an integrated circuit chip module with stiffening frame and orthogonal heat spreader202110,842,043Fabricating coolant-cooled heat sinks with internal thermally-conductive fins202010,757,833Cooling structure for electronic boards202010,593,564Lid attach optimization to limit electronic package warpage202010,566,215Method of fabricating a chip module with stiffening frame and orthogonal heat spreader202010,541,156Multi integrated circuit chip carrier package202010,542,636Cooling structure for electronic boards202010,424,494Chip module with stiffening frame and orthogonal heat spreader201910,381,276Test cell for laminate and method201910,332,813Lid attach optimization to limit electronic package warpage201910,249,548Test cell for laminate and method201910,172,258Cooling structure for electronic boards201910,090,173Method of fabricating a chip module with stiffening frame and directional heat spreader201810,083,886Lid attach optimization to limit electronic package warpage201810,049,896Lid attach optimization to limit electronic package warpage20189,947,603Lid attach optimization to limit electronic package warpage20189,721,870'Cooling structure for electronic boards'20179,583,408'Reducing directional stress in an orthotropic encapsulation member of an electronic package'20179,437,515'Heat spreading layer with high thermal conductivity'20169,366,591'Determining magnitude of compressive loading'20169,153,460'Heatsink attachment module'20159,105,500'Non-hermetic sealed multi-chip module package'20159,087,834'Multichip electronic packages and methods of manufacture'20159,066,460'Disassemblable electronic assembly with leak-inhibiting coolant capillaries'20158,937,810'Electronic assembly with detachable coolant manifold and coolant-cooled electronic module'20158,906,809'Multichip electronic packages and methods of manufacture'20148,900,927'Multichip electronic packages and methods of manufacture'20148,860,206'Multichip electronic packages and methods of manufacture'20148,823,164'Heatsink attachment module'20148,794,079'Determining magnitude of compressive loading'20148,717,043'Determining thermal interface material (TIM) thickness change'20148,693,200'Semiconductor device cooling module'20148,592,970'Multichip electronic packages and methods of manufacture'20138,587,114'Multichip electronic packages and methods of manufacture'20138,445,331'Multichip electronic packages and methods of manufacture'20137,928,562'Segmentation of a die stack for 3D packaging thermal management'20117,834,442'Electronic package method and structure with cure-melt hierarchy'20107,803,664'Apparatus and methods for cooling semiconductor integrated circuit package structures'20107,768,121'Apparatus and methods for cooling semiconductor integrated circuit package structures'20107,733,655'Lid edge capping load'20107,443,026'IC chip package having force-adjustable member between stiffener and printed circuit board'20087,436,057'Elastomer interposer with voids in a compressive loading system'20087,394,659'Apparatus and methods for cooling semiconductor integrated circuit package structures'20087,288,839'Apparatus and methods for cooling semiconductor integrated circuit package structures'20077,250,576'Chip package having chip extension and method'20076,964,885'Stress resistant land grid array (LGA) module and method of forming the same'20056,955,543'Method and apparatus to form a reworkable seal on an electronic module'20056,774,482'Chip cooling'20046,740,959'EMI shielding for semiconductor chip carriers'20046,703,560'Stress resistant land grid array (LGA) module and method of forming the same'20046,657,864'High density thermal solution for direct attach modules'20036,413,353'Method for direct attachment of a chip to a cooling member'20026,191,480'Universal land grid array socket engagement mechanism'20015,533,256'Method for directly joining a chip to a heat sink'19965,471,027'Method for forming chip carrier with a single protective encapsulant'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995–2021Patents assigned to IBM (57)· patent assignee history
1995–2021Based in Poughkeepsie, NY, US· patent location history
2013–2015Patents assigned to ZITZ JEFFREY A (11)· patent assignee history
2013–2014Patents assigned to SIKKA KAMAL K (6)· patent assignee history
2013–2015Patents assigned to TOY HILTON T (6)· patent assignee history
2014–2015Patents assigned to BODENWEBER PAUL F (3)· patent assignee history
2014Based in Hopewell Junction, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 57 | 1995–2021 |
| ZITZ JEFFREY Aself | 11 | 2013–2015 |
| SIKKA KAMAL K | 6 | 2013–2014 |
| TOY HILTON T | 6 | 2013–2015 |
| BODENWEBER PAUL F | 3 | 2014–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Poughkeepsie, New York, US | 55 | 1995–2021 |
| Hopewell Junction, New York, US | 2 | 2014 |