Inventor
Christian Zoellin
Inventor
Weinstadt, DE
Overview
Patents· 35 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing66%
G01RMeasuring electric variables14%
H03MCoding9%
H04LTransmission of digital information, e.g. telegraphic communication5%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
G11CStatic stores2%
PatentTitleYear
11,010,298Reducing cache transfer overhead in a system202110,983,797Program instruction scheduling202110,956,440Compressing a plurality of documents202110,949,212Saving and restoring machine state between multiple executions of an instruction202110,936,318Tagged indirect branch predictor (TIP)202110,831,502Migration of partially completed instructions202010,831,478Sort and merge instruction for a general-purpose processor202010,831,503Saving and restoring machine state between multiple executions of an instruction202010,824,426Generating and verifying hardware instruction traces including memory data contents202010,740,104Tagging target branch predictors with context with index modification and late stop fetch on tag mismatch202010,725,738Adaptive sort accelerator sharing first level processor cache202010,719,294Hardware sort accelerator sharing first level processor cache202010,691,412Parallel sort accelerator sharing first level processor cache202010,671,532Reducing cache transfer overhead in a system202010,585,800Reducing cache transfer overhead in a system202010,579,332Hardware sort accelerator sharing first level processor cache202010,579,525Reducing cache transfer overhead in a system202010,521,506Memory preserving parse tree based compression with entropy coding201910,496,405Generating and verifying hardware instruction traces including memory data contents201910,360,030Efficient pointer load and format201910,353,707Efficient pointer load and format201910,348,506Determination of state of padding operation201910,331,446Generating and verifying hardware instruction traces including memory data contents201910,317,465Integrated circuit chip and a method for testing the same201910,303,759Memory preserving parse tree based compression with entropy coding201910,235,138Instruction to provide true random numbers201910,169,041Efficient pointer load and format201910,006,965Integrated circuit chip and a method for testing the same20189,891,272'Module testing utilizing wafer probe test equipment'20189,885,748'Module testing utilizing wafer probe test equipment'20189,716,515'Method for detecting end of record in variable length coded bit stream'20179,680,653'Cipher message with authentication instruction'20179,679,665'Method for performing built-in self-tests'20179,506,986'Integrated circuit chip and a method for testing the same'20169,171,110'Accelerating functional verification of an integrated circuit'2015Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2015–2021Patents assigned to IBM (35)· patent assignee history
2015Patents assigned to DEINDL MICHAEL (1)· patent assignee history
2015Patents assigned to RUEDINGER JEFFREY JOSEPH (1)· patent assignee history
2015Patents assigned to ZOELLIN CHRISTIAN G (1)· patent assignee history
2015Based in Yorktown Heights, NY, US· patent location history
2016–2021Based in Weinstadt, DE· patent location history
2017–2019Based in Boeblingen, DE· patent location history
2020–2021Based in Austin, TX, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 35 | 2015–2021 |
| DEINDL MICHAEL | 1 | 2015 |
| RUEDINGER JEFFREY JOSEPH | 1 | 2015 |
| ZOELLIN CHRISTIAN Gself | 1 | 2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Weinstadt, DE | 21 | 2016–2021 |
| Austin, Texas, US | 7 | 2020–2021 |
| Boeblingen, DE | 6 | 2017–2019 |
| Yorktown Heights, New York, US | 1 | 2015 |