Inventor
Szuya LIAO
Inventor
TW
Overview
Patents· 15 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices29%
H01LSemiconductor devices24%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1014%
B82YSpecific uses or applications of nanostructures12%
G11CStatic stores5%
H10BElectronic memory devices5%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%
C07FAcyclic, carbocyclic or heterocyclic compounds containing elements other than carbon, hydrogen, halogen, oxygen, nitrogen, sulfur, selenium or tellurium2%
G06FElectric digital data processing2%
H03KPulse technique2%
PatentTitleYear
12,593,681Semiconductor device including dielectrics made of porous organic frameworks, and method of fabricating the same202612,581,745Integrated circuit and system for fabricating the same202612,520,562Semiconductor device with germanium-based channel202612,520,577Complementary field effect transistor with hybrid nanostructure202612,484,253Metal features of a semiconductor device and methods for forming the same202512,437,806Semiconductor device and operating method thereof202512,424,275Static random-access memory (SRAM) device and related SRAM-based compute-in-memory devices202512,417,941Isolation structures in semiconductor devices202512,363,992Semiconductor device and manufacturing method thereof202512,336,235Semiconductor device having isolation structure formed of low-k dielectric material and method for forming the same202512,334,350Semiconductor device and method of manufacture202512,218,225Radical treatment in supercritical fluid for gate dielectric quality improvement to CFET structure202512,132,079Bonding and isolation techniques for stacked transistor structures202412,131,954Selective epitaxy process for the formation of CFET local interconnection202412,119,271Backside gate contact, backside gate etch stop layer, and methods of forming same2024Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2024–2026Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (15)· patent assignee history
2024–2026Based in TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 15 | 2024–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| TW | 15 | 2024–2026 |