Inventor
Dhivya Jeganathan
Inventor
Austin, TX, US
Overview
Patents· 17 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing63%
G11CStatic stores15%
H03MCoding11%
G05BControl or regulating systems in general4%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes4%
Y02PClimate change mitigation technologies in the production or processing of goods4%
PatentTitleYear
11,086,630Finish exception handling of an instruction completion table202110,719,056Merging status and control data in a reservation station202010,649,779Variable latency pipe for interleaving instruction tags in a microprocessor202010,613,868Variable latency pipe for interleaving instruction tags in a microprocessor202010,489,253On-demand GPR ECC error detection and scrubbing for a multi-slice microprocessor201910,445,100Broadcasting messages between execution slices for issued instructions indicating when execution results are ready201910,176,038Partial ECC mechanism for a byte-write capable register201910,031,757Operation of a multi-slice processor implementing a mechanism to overcome a system hang20189,983,879Operation of a multi-slice processor implementing dynamic switching of instruction issuance order20189,985,656Generating ECC values for byte-write capable registers20189,985,655Generating ECC values for byte-write capable registers20189,959,123Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor20189,928,073'Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor'20189,921,833'Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor'20189,858,078'Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor'20189,766,975'Partial ECC handling for a byte-write capable register'20179,639,418'Parity protection of a register'2017Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2017–2021Patents assigned to IBM (17)· patent assignee history
2017–2021Based in Austin, TX, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 17 | 2017–2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 17 | 2017–2021 |