LexDanaLexDanabeta
Inventor

Adam R. Talcott

Inventor
San Jose, CA, US

Overview

26→
Patents
1998–2014
Patent span
Physics
Primary field (CPC G)

Patents· 26 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing96%
G11CStatic stores4%
PatentTitleYear
8,826,241'Instruction sampling in a multi-threaded processor'20148,762,951'Apparatus and method for profiling system events in a fine grain multi-threaded multi-core processor'20147,827,383'Efficient on-chip accelerator interfaces to reduce software overhead'20107,809,895'Low overhead access to shared on-chip hardware accelerator with memory-based interfaces'20107,707,554'Associating data source information with runtime events'20107,096,390'Sampling mechanism including instruction filtering'20066,948,055'Accuracy of multiple branch prediction schemes'20056,934,830'Method and apparatus for reducing register file access times in pipelined processors'20056,738,897'Incorporating local branch history when predicting multiple conditional branch outcomes'20046,615,343'Mechanism for delivering precise exceptions in an out-of-order processor with speculative execution'20036,510,511'Methods and apparatus for branch prediction using hybrid history with index sharing'20036,330,662'Apparatus including a fetch unit to include branch history information to increase performance of multi-cylce pipelined branch prediction structures'20016,289,441'Method and apparatus for performing multiple branch predictions per cycle'20016,272,623'Methods and apparatus for branch prediction using hybrid history with index sharing'20016,256,729'Method and apparatus for resolving multiple branches'20016,256,709'Method for storing data in two-way set associative odd and even banks of a cache memory'20016,134,654'Bi-level branch target prediction scheme with fetch address prediction'20006,115,810'Bi-level branch target prediction scheme with mux select prediction'20005,964,869'Instruction fetch mechanism with simultaneous prediction of control-flow instructions'19995,941,985'Branch instruction prediction method'19995,938,761'Method and apparatus for branch target prediction'19995,935,238'Selection from multiple fetch addresses generated concurrently including predicted and actual target by control-flow instructions in current and previous instruction bundles'19995,875,325'Processor having reduced branch history table size through global branch history compression and method of branch prediction utilizing compressed global branch history'19995,857,098'Branch instruction prediction apparatus'19995,854,761'Cache memory array which stores two-way set associative data'19985,796,998'Apparatus and method for performing branch target address calculation and branch prediciton in parallel in an information handling system'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998–2006Patents assigned to SUN MICROSYSTEMS INC (18)· patent assignee history
1998–1999Patents assigned to IBM (2)· patent assignee history
1998–2001Based in Santa Clara, CA, US· patent location history
2000–2014Based in San Jose, CA, US· patent location history
2010–2014Patents assigned to ORACLE AMERICA INC (5)· patent assignee history
2010–2014Based in Los Altos, CA, US· patent location history
2014Patents assigned to TALCOTT ADAM R (2)· patent assignee history
2014Patents assigned to KOSCHE NICOLAI (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
SUN MICROSYSTEMS INC181998–2006
ORACLE AMERICA INC52010–2014
IBM21998–1999
TALCOTT ADAM Rself22014
KOSCHE NICOLAI12014
Locations
LocationPatentsSpan
San Jose, California, US142000–2014
Santa Clara, California, US91998–2001
Los Altos, California, US32010–2014