Inventor

Martin Eckert

Inventor
Moetzingen, DE

Overview

54→
Patents
2002–2021
Patent span
Physics
Primary field (CPC G)

Patents· 54 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G01Rprimary
G01RMeasuring electric variables21%
G06FElectric digital data processing10%
G11CStatic stores9%
Y10TTechnical subjects covered by former us classification9%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h106%
F16HGearing5%
H01LSemiconductor devices5%
F16MFrames, casings or beds of engines, machines or apparatus, not specific to engines, machines or apparatus provided for elsewhere4%
G01BMeasuring length, thickness or similar linear dimensions4%
PatentTitleYear
10,955,440Probe card alignment202110,684,930Functional testing of high-speed serial links202010,614,884Content addressable memory with match hit quality indication202010,605,649Adjustable load transmitter202010,527,649Probe card alignment202010,422,817Probe card alignment201910,345,136Adjustable load transmitter201910,347,337Content addressable memory with match hit quality indication201910,146,144Adjustable load transmitter201810,114,069Method for electrical testing of a 3-D chip stack201810,114,914Layout effect characterization for integrated circuits201810,082,526Probe card alignment201810,082,419Adjustable load transmitter201810,056,346Chip attach frame20189,977,053Wafer probe alignment20189,927,463'Wafer probe alignment'20189,904,748'Layout effect characterization for integrated circuits'20189,891,272'Module testing utilizing wafer probe test equipment'20189,892,789'Content addressable memory with match hit quality indication'20189,885,748'Module testing utilizing wafer probe test equipment'20189,804,231'Power noise histogram of a computer system'20179,740,813'Layout effect characterization for integrated circuits'20179,709,625'Measuring power consumption in an integrated circuit'20179,686,895'Chip attach frame'20179,679,665'Method for performing built-in self-tests'20179,627,090'RAM at speed flexible timing and setup control'20179,627,017'RAM at speed flexible timing and setup control'20179,620,244'Determining categories for memory fail conditions'20179,496,188'Soldering three dimensional integrated circuits'20169,401,222'Determining categories for memory fail conditions'20169,300,793'Provision of a personalized indicator datum when setting up a telecommunication'20169,250,289'System for electrical testing and manufacturing of a 3-D chip stack and method'20169,183,833'Method and system for adapting interactions'20159,094,306'Network power fault detection'20159,008,196'Updating interface settings for an interface'20158,866,504'Determining local voltage in an electronic system'20148,659,310'Method and system for performing self-tests in an electronic system'20148,535,956'Chip attach frame'20138,510,072'Detecting an unstable input to an IC'20138,253,552'Method and device for configuring functional capabilities in a data processing system'20128,180,142'Test fail analysis on VLSI chips'20128,126,703'Method, spoken dialog system, and telecommunications terminal device for multilingual speech output'20127,949,517'Dialogue system with logical evaluation for language identification in speech recognition'20117,747,428'Visibly distinguishing portions of compound words'20107,559,692'X-ray sensitive camera comprising two image receivers and X-ray device'20097,466,716'Reducing latency in a channel adapter by accelerated I/O control block processing'20087,322,746'X-ray sensitive camera comprising two image receivers and X-ray device'20087,188,541'Transmission mechanism comprising a shifting device'20077,092,310'Memory array with multiple read ports'20067,051,609'Transmission mechanism comprising a shifting device'20066,997,075'Motor vehicle with a gearbox and method for operating a motor vehicle'20066,698,302'Method of keeping track of the operating position of an actuator in an automated gear-shift transmission'20046,695,747'Transmission mechanism comprising a shifting device'20046,341,093'SOI array sense and write margin qualification'2002

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2002–2021Patents assigned to IBM (41)· patent assignee history
2002–2008Based in Jettingen, DE· patent location history
2004–2007Patents assigned to LUK LAMELLEN & KUPPLUNGSBAU (5)· patent assignee history
2004–2007Based in Achern, DE· patent location history
2011–2016Patents assigned to DEUTSCHE TELEKOM AG (4)· patent assignee history
2011–2016Based in Berlin, DE· patent location history
2012–2017Patents assigned to ECKERT MARTIN (11)· patent assignee history
2012–2021Based in Moetzingen, DE· patent location history
2012–2018Based in Boeblingen, DE· patent location history
2014–2017Patents assigned to FRECH ROLAND (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
IBM412002–2021
ECKERT MARTINself112012–2017
LUK LAMELLEN & KUPPLUNGSBAU52004–2007
DEUTSCHE TELEKOM AG42011–2016
FRECH ROLAND32014–2017
Locations
LocationPatentsSpan
Moetzingen, DE302012–2021
Boeblingen, DE92012–2018
Berlin, DE42011–2016
Achern, DE42004–2007
Jettingen, DE32002–2008