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Inventor

Naoki Kuroda

Inventor
Kyoto, JP

Overview

33→
Patents
1981–2019
Patent span
Physics
Primary field (CPC G)

Patents· 33 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores56%
Y10TTechnical subjects covered by former us classification7%
B21DWorking or processing of sheet metal or metal tubes, rods or profiles without essentially removing material5%
H03FAmplifiers5%
H10BElectronic memory devices5%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%
E02FDredging2%
F15BSystems acting by means of fluids in general2%
G06FElectric digital data processing2%
H01BCables2%
PatentTitleYear
10,473,125Hydraulic actuator control circuit20198,830,774'Semiconductor memory device'20148,817,551'Semiconductor memory device'20148,755,217'Semiconductor memory device'20148,164,938'Semiconductor memory device'20127,962,105'RF power module'20117,779,277'Power control for a plurality of internal power supply circuits of a semiconductor integrated circuit'20107,706,756'RF power module'20107,656,732'Semiconductor storage device'20107,561,080'Semiconductor integrated circuit'20097,417,911'Semiconductor memory device having hierarchically structured data lines and precharging means'20087,349,267'Semiconductor memory device'20087,330,386'Semiconductor memory device'20087,254,072'Semiconductor memory device having hierarchically structured data lines and precharging means'20077,183,829'Semiconductor device including a plurality of circuit blocks provided on a chip and having different functions'20077,102,413'Semiconductor integrated circuit device'20067,057,968'Semiconductor integrated circuit device'20067,031,199'Semiconductor memory device'20066,990,043'Semiconductor integrated circuit device having a common DRAM block accessed by a plurality of logic circuits'20066,909,624'Semiconductor memory device and test method thereof'20056,788,565'Semiconductor memory device'20046,751,154'Semiconductor memory device'20046,751,116'Semiconductor memory device'20046,327,210'Semiconductor memory device'20016,243,301'Semiconductor memory device and signal line switching circuit'20016,226,223'Low latency dynamic random access memory'20016,181,620'Semiconductor storage device'20016,169,684'Semiconductor memory device'20016,137,713'Semiconductor storage device'20005,204,653'Electromagnetic induction device with magnetic particles between core segments'19934,979,292'Method of forming filament harness'19904,448,099'Work handling method'19844,297,927'Sheet metal positioning and gripping apparatus and method'1981

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1981–1984Patents assigned to WARNER SWASEY CO (2)· patent assignee history
1981–2010Based in Kyoto, JP· patent location history
1993–2014Based in Osaka, JP· patent location history
2000–2008Patents assigned to MATSUSHITA ELECTRIC INDUSTRIAL CO LTD (19)· patent assignee history
2004–2008Based in Nagaokakyo, JP· patent location history
2009–2014Patents assigned to PANASONIC CORP (7)· patent assignee history
2010–2011Based in Tokyo, JP· patent location history
2012–2014Patents assigned to KURODA NAOKI (2)· patent assignee history
2019Patents assigned to CATERPILLAR SARL (1)· patent assignee history
2019Based in Hyogo, JP· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MATSUSHITA ELECTRIC INDUSTRIAL CO LTD192000–2008
PANASONIC CORP72009–2014
KURODA NAOKIself22012–2014
WARNER SWASEY CO21981–1984
CATERPILLAR SARL12019
Locations
LocationPatentsSpan
Kyoto, JP181981–2010
Osaka, JP71993–2014
Nagaokakyo, JP42004–2008
Tokyo, JP22010–2011
Hyogo, JP12019