Inventor
Jerrell P. Hein
Inventor
Driftwood, TX, US
Overview
Patents· 43 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H04Mprimary
H04MTelephonic communication25%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses19%
H04LTransmission of digital information, e.g. telegraphic communication18%
G11BInformation storage based on relative movement between record carrier and transducer7%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use7%
G06FElectric digital data processing4%
H03KPulse technique4%
H04JMultiplex communication4%
G01RMeasuring electric variables3%
H03MCoding3%
PatentTitleYear
8,532,243'Digital hold in a phase-locked loop'20137,825,708'Dual loop architecture useful for a programmable clock source and clock multiplier applications'20107,643,629'Low voltage sensing and control of battery referenced transistors in subscriber loop applications'20107,486,787'Subscriber line interface circuitry with common base audio isolation stage'20097,453,388'Slice voltage compensation'20087,454,306'Frequency margin testing'20087,450,712'Low voltage sensing and control of battery referenced transistors in subscriber loop applications'20087,436,227'Dual loop architecture useful for a programmable clock source and clock multiplier applications'20087,295,077'Multi-frequency clock synthesizer'20077,288,998'Voltage controlled clock synthesizer'20077,254,230'Subscriber line interface circuitry'20077,227,913'Clock and data recovery circuit without jitter peaking'20077,190,785'Subscriber line interface circuitry'20077,187,241'Calibration of oscillator devices'20077,180,999'Subscriber line interface circuitry'20077,158,633'Method and apparatus for monitoring subscriber loop interface circuitry power dissipation'20077,145,359'Multiple signal format output buffer'20067,064,617'Method and apparatus for temperature compensation'20066,987,424'Narrow band clock multiplier unit'20066,975,723'Architecture for minimum loop current during ringing and caller ID'20056,934,384'Subscriber line interface circuitry'20056,922,469'Separation of ring detection functions across isolation barrier for minimum power'20056,724,891'Integrated modem and line-isolation circuitry and associated method powering caller ID circuitry with power provided across an isolation barrier'20046,686,803'Integrated circuit incorporating circuitry for determining which of at least two possible frequencies is present on an externally provided reference signal and method therefor'20046,567,521'Subscriber loop interface circuitry having bifurcated common mode control'20036,456,712'Separation of ring detection functions across isolation barrier for minimum power'20026,442,271'Digital isolation system with low power mode'20026,408,034'Framed delta sigma data with unlikely delta sigma data patterns'20026,307,891'Method and apparatus for freezing a communication link during a disruptive event'20016,298,133'Telephone line interface architecture using ringer inputs for caller ID data'20016,198,816'Capacitively coupled ring detector with power provided across isolation barrier'20016,141,169'System and method for control of low frequency input levels to an amplifier and compensation of input offsets of the amplifier'20006,111,712'Method to improve the jitter of high frequency phase locked loops used in read channels'20006,104,794'Architecture for minimum loop current during ringing and caller ID'20006,078,444'Read channel auxiliary high precision data conversion'20006,028,727'Method and system to improve single synthesizer setting times for small frequency steps in read channel circuits'20005,990,814'Method and circuit for calibration of flash analog to digital converters'19995,986,830'Read/write channel write precompensation system and method using one or more delay clocks'19995,717,728'Data/clock recovery circuit'19985,150,386'Clock multiplier/jitter attenuator'19924,902,913'Analog comparator'19904,805,198'Clock multiplier/jitter attenuator'19894,595,874'Temperature insensitive CMOS precision current source'1986Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1986Patents assigned to AT & T BELL LAB (1)· patent assignee history
1986Based in Longswamp Township, Berks County, PA, US· patent location history
1989–1992Patents assigned to CRYSTAL SEMICONDUCTOR CORP (2)· patent assignee history
1989–1992Based in West Lawn, PA, US· patent location history
1990Patents assigned to AMERICAN TELEPHONE & TELEGRAPH (1)· patent assignee history
1990Based in Berks, GB· patent location history
1998–2013Based in Driftwood, TX, US· patent location history
1999–2000Patents assigned to CIRRUS LOGIC INC (6)· patent assignee history
2000–2013Patents assigned to SILICON LAB INC (32)· patent assignee history
2002Based in Austin, TX, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SILICON LAB INC | 32 | 2000–2013 |
| CIRRUS LOGIC INC | 6 | 1999–2000 |
| CRYSTAL SEMICONDUCTOR CORP | 2 | 1989–1992 |
| AMERICAN TELEPHONE & TELEGRAPH | 1 | 1990 |
| AT & T BELL LAB | 1 | 1986 |
Locations
| Location | Patents | Span |
|---|---|---|
| Driftwood, Texas, US | 37 | 1998–2013 |
| Austin, Texas, US | 2 | 2002 |
| West Lawn, Pennsylvania, US | 2 | 1989–1992 |
| Berks, GB | 1 | 1990 |
| Longswamp Township, Berks County, Pennsylvania, US | 1 | 1986 |