Inventor

Kerry D. Tedrow

Inventor

Folsom, CA, US

Overview

1994–2021

Patent span

Physics

Primary field (CPC G)

Patents· 63 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores73%

H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems12%

G06FElectric digital data processing7%

G05FSystems for regulating electric or magnetic variables6%

H03KPulse technique1%

H10BElectronic memory devices1%

PatentTitleYear

10,942,873Memory tile access and selection patterns2021 10,748,613Memory sense amplifiers and memory verification methods2020 10,387,338Memory tile access and selection patterns2019 10,147,487Memory sense amplifiers and memory verification methods2018 9,959,220Memory tile access and selection patterns2018 9,799,398'Memory cell verification circuits, memory cell sense circuits and memory cell verification methods'2017 9,626,292'Memory tile access and selection patterns'2017 9,564,181'Memory device comprising double cascode sense amplifiers'2017 9,437,288'Dual mode clock and data scheme for memory programming'2016 9,406,362'Memory tile access and selection patterns'2016 9,311,999'Memory sense amplifiers and memory verification methods'2016 8,804,411'Dual mode clock and data scheme for memory programming'2014 8,259,488'Phase-change memory temperature sensitive detector'2012 8,176,232'Dedicated interface to factory program phase-change memories'2012 8,059,468'Switched bitline VTH sensing for non-volatile memories'2011 7,551,489'Multi-level memory cell sensing'2009 7,525,840'Memory array with pseudo single bit memory cell and method'2009 7,525,865'Control circuit for refreshing voltages in a non-volatile memory during a standby mode and a method thereof'2009 7,319,616'Negatively biasing deselected memory cells'2008 7,313,019'Step voltage generation'2007 7,272,041'Memory array with pseudo single bit memory cell and method'2007 7,176,751'Voltage reference apparatus, method, and system'2007 7,139,205'Apparatuses and methods for pre-charging intermediate nodes for high-speed wordline'2006 7,116,597'High precision reference devices and methods'2006 6,944,065'Method, apparatus, and system to enhance negative voltage switching'2005 6,831,862'Method and apparatus for matched-reference sensing architecture for non-volatile memories'2004 6,788,584'Method, apparatus, and system to enhance negative voltage switching'2004 6,772,273'Block-level read while write method and apparatus'2004 6,700,820'Programming non-volatile memory devices'2004 6,697,282'Reference voltage generator employing large flash memory cells coupled to threshold tuning devices'2004 6,628,108'Method and apparatus to provide a low voltage reference generation'2003 6,597,606'Charging a capacitance of a memory cell and charger'2003 6,515,906'Method and apparatus for matched-reference sensing architecture for non-volatile memories'2003 6,504,760'Charging a capacitance of a memory cell and charger'2003 6,477,091'Method, apparatus, and system to enhance negative voltage switching'2002 6,477,086'Local sensing of non-volatile memory'2002 6,429,732'Oscillator for simultaneously generating multiple clock signals of different frequencies'2002 6,359,814'Negative output voltage charge pump and method therefor'2002 6,359,809'Oscillator for simultaneously generating multiple clock signals of different frequencies'2002 6,075,751'Signal transition detector for asynchronous circuits'2000 5,973,957'Sense amplifier comprising a preamplifier and a differential input latch for flash memories'1999 5,946,258'Pump supply self regulation for flash memory cell pair reference circuit'1999 5,781,473'Variable stage charge pump'1998 5,767,735'Variable stage charge pump'1998 5,732,039'Variable stage charge pump'1998 5,602,794'Variable stage charge pump'1997 5,559,717'High precision voltage detector utilizing flash EEPROM memory cells'1996 5,553,030'Method and apparatus for controlling the output voltage provided by a charge pump circuit'1996 5,553,295'Method and apparatus for regulating the output voltage of negative charge pumps'1996 5,546,042'High precision voltage regulation circuit for programming multiple bit flash memory'1996 5,532,915'Method and apparatus for providing an ultra low power regulated negative charge pump'1996 5,524,266'System having multiple phase boosted charge pump with a plurality of stages'1996 5,497,119'High precision voltage regulation circuit for programming multilevel flash memory'1996 5,455,794'Method and apparatus for controlling the output current provided by a charge pump circuit'1995 5,446,408'Method and apparatus for providing selectable sources of voltage'1995 5,442,586'Method and apparatus for controlling the output current provided by a charge pump circuit'1995 5,432,469'Method and apparatus for a two phase bootstrap charge pump'1995 5,430,402'Method and apparatus for providing selectable sources of voltage'1995 5,426,391'Method and apparatus for providing selectable sources of voltage'1995 5,422,586'Apparatus for a two phase bootstrap charge pump'1995 5,414,669'Method and apparatus for programming and erasing flash EEPROM memory arrays utilizing a charge pump circuit'1995 5,339,272'Precision voltage reference'1994 5,306,963'Address transition detection noise filter in pulse summation circuit for nonvolatile semiconductor memory'1994

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1994–2011Patents assigned to INTEL CORP (49)· patent assignee history

1994–1998Based in Orangevale, CA, US· patent location history

1999–2021Based in Folsom, CA, US· patent location history

2011Patents assigned to HENDRICKSON NICHOLAS T (1)· patent assignee history

2012–2021Patents assigned to MICRON TECHNOLOGY INC (13)· patent assignee history

2012–2014Patents assigned to TEDROW KERRY DEAN (3)· patent assignee history

2012Patents assigned to HENDRICKSON NICHOLAS (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	49	1994–2011
MICRON TECHNOLOGY INC	13	2012–2021
TEDROW KERRY DEANself	3	2012–2014
HENDRICKSON NICHOLAS	1	2012
HENDRICKSON NICHOLAS T	1	2011

Locations

Location	Patents	Span
Folsom, California, US	42	1999–2021
Orangevale, California, US	21	1994–1998