Inventor
Nirmal Ramaswamy
Inventor
Boise, ID, US
Overview
Patents· 46 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices26%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1019%
H10BElectronic memory devices17%
H01LSemiconductor devices9%
H10NElectric solid-state devices not otherwise provided for6%
B82YSpecific uses or applications of nanostructures5%
C23CCoating metallic material4%
G11CStatic stores4%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
PatentTitleYear
10,818,760Memory cells having electrically conductive nanodots and apparatus having such memory cells202010,256,309Memory cells having electrically conductive nanodots201910,141,322Metal floating gate composite 3D NAND memory devices and associated methods20189,691,976'Interfacial cap for electrode contacts in memory cell arrays'20179,343,674'Cross-point memory utilizing Ru/Si diode'20169,306,162'Interfacial cap for electrode contacts in memory cell arrays'20169,202,700'Charge storage nodes with conductive nanodots'20159,029,256'Charge-trap based memory'20158,846,516'Dielectric charge-trapping materials having doped metal sites'20148,803,125'Cross-point memory utilizing Ru/Si diode'20148,796,661'Nonvolatile memory cells and methods of forming nonvolatile memory cell'20148,796,751'Transistors, memory cells and semiconductor constructions'20148,772,856'Charge storage nodes with conductive nanodots'20148,673,706'Methods of forming layers comprising epitaxial silicon'20148,643,082'Thickened sidewall dielectric for memory cell'20148,395,140'Cross-point memory utilizing Ru/Si diode'20138,357,970'Multi-level charge storage transistors and associated methods'20138,258,034'Charge-trap based memory'20128,203,179'Device having complex oxide nanodots'20128,058,140'Thickened sidewall dielectric for memory cell'20118,035,129'Integrated circuitry'20117,989,289'Floating gate structures'20117,943,507'Atomic layer deposition systems and methods including silicon-containing tantalum precursor compounds'20117,898,017'Floating-gate memory cell and memory device and electronic system therewith'20117,851,307'Method of forming complex oxide nanodots for a charge trap'20107,807,535'Methods of forming layers comprising epitaxial silicon'20107,768,036'Integrated circuitry'20107,709,326'Methods of forming layers comprising epitaxial silicon'20107,705,389'Thickened sidewall dielectric for memory cell'20107,662,649'Methods for assessing alignments of substrates within deposition apparatuses; and methods for assessing thicknesses of deposited layers within deposition apparatuses'20107,585,371'Substrate susceptors for receiving semiconductor substrates to be deposited upon'20097,547,617'Semiconductor device including container having epitaxial silicon therein'20097,538,392'Pseudo SOI substrate and associated semiconductor devices'20097,531,395'Methods of forming a layer comprising epitaxial silicon, and methods of forming field effect transistors'20097,528,424'Integrated circuitry'20097,521,356'Atomic layer deposition systems and methods including silicon-containing tantalum precursor compounds'20097,517,758'Method of forming a vertical transistor'20097,439,136'Method of forming a layer comprising epitaxial silicon'20087,390,710'Protection of tunnel dielectric using epitaxial silicon'20087,276,416'Method of forming a vertical transistor'20077,268,023'Method of forming a pseudo SOI substrate and semiconductor devices'20077,253,085'Deposition methods'20077,144,779'Method of forming epitaxial silicon-comprising material'20067,132,355'Method of forming a layer comprising epitaxial silicon and a field effect transistor'20067,115,489'Methods of growing epitaxial silicon'20066,987,055'Methods for deposition of semiconductor material'2006Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2006–2020Patents assigned to MICRON TECHNOLOGY INC (41)· patent assignee history
2006–2020Based in Boise, ID, US· patent location history
2011–2015Patents assigned to RAMASWAMY NIRMAL (11)· patent assignee history
2011–2014Patents assigned to GRAETTINGER TOM (2)· patent assignee history
2011–2018Patents assigned to INTEL CORP (2)· patent assignee history
2012–2015Patents assigned to SANDHU GURTEJ S (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 41 | 2006–2020 |
| RAMASWAMY NIRMALself | 11 | 2011–2015 |
| SANDHU GURTEJ S | 4 | 2012–2015 |
| GRAETTINGER TOM | 2 | 2011–2014 |
| INTEL CORP | 2 | 2011–2018 |
Locations
| Location | Patents | Span |
|---|---|---|
| Boise, ID, US | 46 | 2006–2020 |