Inventor
CYPRIAN EMEKA UZOH
Inventor
US
Overview
Patents· 85 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices34%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1034%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%
B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems3%
B81BMicrostructural devices or systems, e.g. micromechanical devices3%
H10DInorganic electric semiconductor devices3%
H05KPrinted circuits2%
H10HInorganic light-emitting semiconductor devices having potential barriers2%
C23CCoating metallic material1%
C25DProcesses for the electrolytic or electrophoretic production of coatings1%
PatentTitleYear
12,598,962System and method for bonding transparent conductor substrates202612,563,749Stacked electronic devices202612,564,086Structures for low temperature bonding using nanoparticles202612,557,615Methods for bonding semiconductor elements202612,550,799Direct bonding methods and structures202612,545,010Directly bonded metal structures having oxide layers therein202612,512,425Expansion controlled structure for direct bonding and method of forming same202512,506,114Directly bonded metal structures having aluminum features and methods of preparing same202512,482,776Metal pads over TSV202512,456,662Structures with through-substrate vias and methods for forming the same202512,431,460Die processing202512,424,584Direct bonding methods and structures202512,406,975Techniques for processing devices202512,381,117Through-dielectric-vias (TDVs) for 3D integrated circuits in silicon202512,381,119Seal for microelectronic assembly202512,381,173Direct hybrid bonding of substrates having microelectronic components with different profiles and/or pitches at the bonding interface202512,374,556Processing stacked substrates202512,341,125Dimension compensation control for directly bonded structures202512,322,667Seal for microelectronic assembly202512,322,650Diffusion barrier for interconnects202512,300,661Reliable hybrid bonded apparatus202512,272,677Direct bonded stack structures for increased reliability and improved yield in microelectronics202512,266,640Molded direct bonded and interconnected stack202512,266,650Stacked dies and methods for forming bonded structures202512,211,809Structure with conductive feature and method of forming same202512,205,926TSV as pad202512,199,082Method of direct-bonded optoelectronic devices202512,198,981Diffusion barrier collar for interconnects202512,191,233Embedded cooling systems and methods of manufacturing embedded cooling systems202512,176,263Integrated cooling assembly including coolant channel on the backside semiconductor device202412,166,024Direct-bonded LED arrays drivers202412,154,880Method and structures for low temperature device bonding202412,136,605Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics and method for forming the same202412,132,020Low temperature bonded structures202412,125,784Interconnect structures202412,113,056Stacked dies and methods for forming bonded structures202412,100,676Low temperature bonded structures202412,087,629Through-dielectric-vias (TDVs) for 3D integrated circuits in silicon202412,080,672Direct gang bonding methods including directly bonding first element to second element to form bonded structure without adhesive202412,068,278Processed stacked dies202412,051,621Microelectronic assembly from processed substrate202412,046,571Low temperature bonded structures202412,033,943Laterally unconfined structure202412,027,487Structures for low temperature bonding using nanoparticles202412,009,338Dimension compensation control for directly bonded structures202411,999,001Advanced device assembly structures and methods2024RE049987Multiple plated via arrays of different wire heights on a same substrate202411,973,056Methods for low temperature bonding using nanoparticles202411,967,575Bond enhancement structure in microelectronics for trapping contaminants during direct-bonding processes202411,955,463Direct bonded stack structures for increased reliability and improved yield in microelectronics202411,955,393Structures for bonding elements including conductive interface features202411,955,445Metal pads over TSV202411,908,739Flat metal features for microelectronics applications202411,894,326Multi-metal contact structure202411,862,604Systems and methods for releveled bump planes for chiplets202411,855,064Techniques for processing devices202311,837,582Molded direct bonded and interconnected stack202311,837,596Stacked dies and methods for forming bonded structures202311,764,189Molded direct bonded and interconnected stack202311,756,880Interconnect structures202311,749,645TSV as pad202311,742,314Reliable hybrid bonded apparatus202311,742,315Die processing202311,735,523Laterally unconfined structure202311,715,730Direct-bonded LED arrays including optical elements configured to transmit optical signals from LED elements202311,710,718Structures and methods for low temperature bonding using nanoparticles202311,694,925Diffusion barrier collar for interconnects202311,658,173Stacked dies and methods for forming bonded structures202311,652,083Processed stacked dies202311,552,041Chemical mechanical polishing for hybrid bonding202311,515,279Low temperature bonded structures202211,417,576Seal for microelectronic assembly202211,393,779Large metal pads over TSV202211,367,652Microelectronic assembly from processed substrate202211,348,898Systems and methods for releveled bump planes for chiplets202211,348,801Processing stacked substrates202211,329,034Direct-bonded LED structure contacts and substrate contacts202211,296,053Direct bonded stack structures for increased reliability and improved yield in microelectronics202211,296,044Bond enhancement structure in microelectronics for trapping contaminants during direct-bonding processes202211,257,727Seal for microelectronic assembly202211,244,916Low temperature bonded structures202211,244,920Method and structures for low temperature device bonding202211,195,748Interconnect structures and methods for forming same202111,158,606Molded direct bonded and interconnected stack202111,158,573Interconnect structures2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2022Patents assigned to INVENSAS BONDING TECH INC (11)· patent assignee history
2021–2022Patents assigned to INVENSAS CORP (2)· patent assignee history
2021–2026Based in US· patent location history
2022–2026Patents assigned to ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC (56)· patent assignee history
2023–2026Patents assigned to ADEIA SEMICONDUCTOR TECH LLC (12)· patent assignee history
2026Patents assigned to ADEIA SEMICONDUCTOR BONDING TECH INC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC | 56 | 2022–2026 |
| ADEIA SEMICONDUCTOR TECH LLC | 12 | 2023–2026 |
| INVENSAS BONDING TECH INC | 11 | 2021–2022 |
| INVENSAS CORP | 2 | 2021–2022 |
| ADEIA SEMICONDUCTOR BONDING TECH INC | 1 | 2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 85 | 2021–2026 |