Inventor

Charles F. Webb

Inventor

Wappingers Falls, NY, US

Overview

1979–2021

Patent span

Physics

Primary field (CPC G)

Patents· 101 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing95%

LOCD12%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%

A47LDomestic washing or cleaning1%

PatentTitleYear

10,977,190Dynamic address translation with access control in an emulator environment2021 10,970,224Operational context subspaces2021 10,884,946Memory state indicator check operations2021 10,884,945Memory state indicator check operations2021 10,635,307Memory state indicator2020 10,635,308Memory state indicator2020 10,423,539Dynamic address translation with access control in an emulator environment2019 10,338,923Branch prediction path wrong guess instruction2019 9,934,159Dynamic address translation with fetch protection in an emulated environment2018 9,921,964'Demote instruction for relinquishing cache line ownership'2018 9,921,965'Demote instruction for relinquishing cache line ownership'2018 9,619,384'Demote instruction for relinquishing cache line ownership'2017 9,612,969'Demote instruction for relinquishing cache line ownership'2017 9,501,416'Demote instruction for relinquishing cache line ownership'2016 9,471,503'Demote instruction for relinquishing cache line ownership'2016 9,411,599'Operand fetching control as a function of branch confidence'2016 9,378,128'Dynamic address translation with fetch protection in an emulated environment'2016 9,311,238'Demote instruction for relinquishing cache line ownership'2016 9,250,915'Operand fetching control as a function of branch confidence'2016 9,244,856'Dynamic address translation with translation table entry format control for identifying format of the translation table entry'2016 9,052,889'Load pair disjoint facility and instruction therefor'2015 9,021,225'Dynamic address translation with fetch protection in an emulated environment'2015 9,003,134'Emulation of a dynamic address translation with change record override on a machine of another architecture'2015 8,880,805'Computer system having cache subsystem performing demote requests'2014 8,862,834'Shared memory translation facility'2014 8,850,166'Load pair disjoint facility and instruction therefore'2014 8,677,098'Dynamic address translation with fetch protection'2014 8,631,216'Dynamic address translation with change record override'2014 8,621,180'Dynamic address translation with translation table entry format control for identifying format of the translation table entry'2013 8,549,255'Microprocessor, method and computer program product for direct page prefetch in millicode capable computer system'2013 8,527,715'Providing a shared memory translation facility'2013 8,407,453'Facilitating processing in a computing environment using an extended drain instruction'2013 8,380,907'Method, system and computer program product for providing filtering of GUEST2 quiesce requests'2013 8,131,982'Branch prediction instructions having mask values involving unloading and loading branch history data'2012 8,117,417'Dynamic address translation with change record override'2012 8,112,174'Processor, method and computer program product for fast selective invalidation of translation lookaside buffer'2012 8,103,851'Dynamic address translation with translation table entry format control for indentifying format of the translation table entry'2012 8,078,843'Facilitating processing in a computing environment using an extended drain instruction'2011 8,037,278'Dynamic address translation with format control'2011 8,032,709'System, method and computer program product for handling shared cache lines in a multi-processor environment'2011 8,019,964'Dynamic address translation with DAT protection'2011 7,971,034'Reduced overhead address mode change management in a pipelined, recycling microprocessor'2011 7,966,453'Method and apparatus for active software disown of cache line\'s exlusive rights'2011 7,966,474'System, method and computer program product for translating storage elements'2011 7,953,932'System and method for avoiding deadlocks when performing storage updates in a multi-processor environment'2011 7,882,338'Method, system and computer program product for an implicit predicted return from a predicted subroutine'2011 7,712,076'Register indirect access of program floating point registers by millicode'2010 7,478,185'Directly initiating by external adapters the setting of interruption initiatives'2009 6,952,763'Write before read interlock for recovery unit operands'2005 6,865,645'Program store compare handling between instruction and operand caches'2005 6,775,789'Method, system and program products for generating sequence values that are unique across operating system images'2004 6,751,708'Method for ensuring that a line is present in an instruction cache'2004 6,671,793'Method and system for managing the result from a translator co-processor in a pipelined processor'2003 6,662,296'Method and system for testing millicode branch points'2003 6,560,687'Method of implementing a translation lookaside buffer with support for a real space control'2003 6,490,689'Managing instruction execution in order to accommodate a physical clock value in a clock representation'2002 6,233,655'Method for Quad-word Storing into 2-way interleaved L1 cache'2001 6,125,444'Millimode capable computer system providing global branch history table disables and separate millicode disables which enable millicode disable to be turned off for some sections of code execution but not disabled for all'2000 6,119,219'System serialization with early release of individual processor'2000 6,108,776'Globally or selectively disabling branch history table operations during sensitive portion of millicode routine in millimode supporting computer'2000 6,105,126'Address bit decoding for same adder circuitry for RXE instruction format with same XBD location as RX format and dis-jointed extended operation code'2000 6,105,109'System speed loading of a writable cache code array'2000 6,088,791'Computer processor system for implementing the ESA/390 STOSM and STNSM instructions without serialization or artificially extending processor execution time'2000 6,088,792'Avoiding processor serialization after an S/390 SPKA instruction'2000 6,085,313'Computer processor system for executing RXE format floating point instructions'2000 6,079,013'Multiprocessor serialization with early release of processors'2000 6,067,617'Specialized millicode instructions for packed decimal division'2000 6,058,470'Specialized millicode instruction for translate and test'2000 6,055,624'Millicode flags with specialized update and branch instructions'2000 6,055,623'Specialized millicode instruction for editing functions'2000 6,035,392'Computer with optimizing hardware for conditional hedge fetching into cache storage'2000 6,026,488'Method for conditional hedge fetching into cache storage'2000 5,819,078'Addressing extended memory using millicode by concatenating a small millicode address and address extension data'1998 5,802,359'Mapping processor state into a millicode addressable processor state register array'1998 5,790,844'Millicode load and test access instruction that blocks interrupts in response to access exceptions'1998 5,754,810'Specialized millicode instruction for certain decimal operations'1998 5,748,951'Specialized millicode instructions which reduce cycle time and number of instructions necessary to perform complex operations'1998 5,713,035'Linking program access register number with millicode operand access'1998 5,694,587'Specialized millicode instructions for test PSW validity, load with access test, and character translation assist'1997 5,694,617'System for prioritizing quiesce requests and recovering from a quiescent state in a multiprocessing system with a milli-mode operation'1997 5,687,106'Implementation of binary floating point using hexadecimal floating point unit'1997 5,684,975'Method for use in translating virtual addresses into absolute addresses'1997 5,680,598'Millicode extended memory addressing using operand access control register to control extended address concatenation'1997 5,673,391'Hardware retry trap for millicoded processor'1997 5,649,155'Cache memory accessed by continuation requests'1997 5,649,140'System for use in translating virtual addresses into absolute addresses'1997 5,625,808'Read only store as part of cache store for storing frequently used millicode instructions'1997 5,621,909'Specialized millicode instruction for range checking'1997 5,611,062'Specialized millicode instruction for string operations'1997 5,568,631'Multiprocessor system with a shared control store accessed with predicted addresses'1996 5,504,859'Data processor with enhanced error recovery'1996 5,495,590'Checkpoint synchronization with instruction overlap enabled'1996 5,495,587'Method for processing checkpoint instructions to allow concurrent execution of overlapping instructions'1996 5,461,721'System for transferring data between I/O devices and main or expanded storage under dynamic control of independent indirect address words (IDAWs)'1995 5,371,867'Method of using small addresses to access any guest zone in a large memory'1994 5,345,567'System and method for modifying program status word system mask, system access key, and address space code with overlap enabled'1994 5,276,882'Subroutine return through branch history table'1994 5,257,354'System for monitoring and undoing execution of instructions beyond a serialization point upon occurrence of in-correct results'1993 4,167,799'Carpet cleaning machine'1979 D0252150'Carpet cleaning apparatus'1979 D0252151'Carpet cleaning apparatus'1979

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1979–2019Patents assigned to WEBB CHARLES F (18)· patent assignee history

1979Based in Phoenix, AZ, US· patent location history

1993–2021Patents assigned to IBM (97)· patent assignee history

1993–2005Based in Poughkeepsie, NY, US· patent location history

2004–2021Based in Wappingers Falls, NY, US· patent location history

2011–2014Patents assigned to SLEGEL TIMOTHY J (7)· patent assignee history

2012–2014Patents assigned to HELLER LISA C (7)· patent assignee history

2012–2014Patents assigned to OSISEK DAMIAN L (7)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	97	1993–2021
WEBB CHARLES Fself	18	1979–2019
HELLER LISA C	7	2012–2014
OSISEK DAMIAN L	7	2012–2014
SLEGEL TIMOTHY J	7	2011–2014

Locations

Location	Patents	Span
Wappingers Falls, New York, US	49	2004–2021
Poughkeepsie, New York, US	49	1993–2005
Phoenix, AZ, US	3	1979