Inventor
Chin Chuan Neo
Inventor
Singapore, SG
Overview
Patents· 6 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices31%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1031%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices8%
H10DInorganic electric semiconductor devices8%
H10NElectric solid-state devices not otherwise provided for8%
PatentTitleYear
10,062,733Integrated circuits with magnetic tunnel junction memory cells and methods for producing the same20189,917,027'Integrated circuits with aluminum via structures and methods for fabricating the same'20189,805,971'Method of forming a via contact'20179,520,299'Etch bias control'20167,372,156'Method to fabricate aligned dual damascene openings'20086,967,156'Method to fabricate aligned dual damascene openings'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2008Patents assigned to CHARTERED SEMICONDUCTOR MFG (2)· patent assignee history
2005–2018Based in Singapore, SG· patent location history
2016–2018Patents assigned to GLOBALFOUNDRIES SG PTE LTD (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| GLOBALFOUNDRIES SG PTE LTD | 4 | 2016–2018 |
| CHARTERED SEMICONDUCTOR MFG | 2 | 2005–2008 |
Locations
| Location | Patents | Span |
|---|---|---|
| Singapore, SG | 6 | 2005–2018 |