Inventor
Todd A. Randazzo
Inventor
Colorado Springs, CO, US
Overview
Patents· 49 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices35%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
H03KPulse technique9%
G11CStatic stores8%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%
H10BElectronic memory devices6%
G01TMeasurement of nuclear or x-radiation4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
C23CCoating metallic material3%
G01KMeasuring temperature3%
PatentTitleYear
8,912,818'High speed multiple memory interface I/O cell'20148,399,845'Neutron detector cell efficiency'20138,324,927'High speed multiple memory interface I/O cell'20128,315,588'Resistive voltage-down regulator for integrated circuit receivers'20128,310,021'Neutron detector with wafer-to-wafer bonding'20128,153,985'Neutron detector cell efficiency'20127,948,275'Transceiver with fault tolerant driver'20117,876,123'High speed multiple memory interface I/O cell'20117,868,362'SOI on package hypersensitive sensor'20117,457,090'Use of a known common-mode voltage for input overvoltage protection in pseudo-differential receivers'20087,180,360'Method and apparatus for summing DC voltages'20077,176,082'Analog capacitor in dual damascene process'20076,931,560'Programmable transmit SCSI equalization'20056,924,689'Level shifter reference generator'20056,855,586'Low voltage breakdown element for ESD trigger device'20056,825,546'CMOS varactor with constant dC/dV characteristic'20046,822,282'Analog capacitor in dual damascene process'20046,803,801'CMOS level shifters using native devices'20046,794,310'Method and apparatus for determining temperature of a semiconductor wafer during fabrication thereof'20046,710,990'Low voltage breakdown element for ESD trigger device'20046,621,299'Control circuit for power'20036,614,283'Voltage level shifter'20036,596,579'Method of forming analog capacitor dual damascene process'20036,587,322'Swapped drain structures for electrostatic discharge protection'20036,545,305'Linear capacitor and process for making same'20036,514,824'Semiconductor device with a pair of transistors having dual work function gate electrodes'20036,501,318'High speed input buffer circuit'20026,359,314'Swapped drain structures for electrostatic discharge protection'20026,342,734'Interconnect-integrated metal-insulator-metal capacitor and method of fabricating same'20026,328,802'Method and apparatus for determining temperature of a semiconductor wafer during fabrication thereof'20016,316,817'MeV implantation to form vertically modulated N+ buried layer in an NPN bipolar transistor'20016,225,178'Radiation hardened field oxide for VLSI sub-micron MOS device'20016,211,555'Semiconductor device with a pair of transistors having dual work function gate electrodes'20016,194,766'Integrated circuit having low voltage and high voltage devices on a common semiconductor substrate'20016,133,077'Formation of high-voltage and low-voltage devices on a semiconductor substrate'20006,130,117'Simple bicmos process for creation of low trigger voltage SCR and zener diode pad protection'20006,093,585'High voltage tolerant thin film transistor'20006,090,656'Linear capacitor and process for making same'2000RE036777'Integration of high performance submicron CMOS and dual-poly non-volatile memory devices using a third polysilicon layer'20006,063,672'NMOS electrostatic discharge protection device and method for CMOS integrated circuit'20005,858,828'Use of MEV implantation to form vertically modulated N+ buried layer in an NPN bipolar transistor'19995,838,616'Gate edge aligned EEPROM transistor'19985,821,572'Simple BICMOS process for creation of low trigger voltage SCR and zener diode pad protection'19985,780,329'Process for fabricating a moderate-depth diffused emitter bipolar transistor in a BICMOS device without using an additional mask'19985,661,687'Drain excluded EPROM cell'19975,648,930'Non-volatile memory which is programmable from a power source'19975,493,142'Input/output transistors with optimized ESD protection'19965,440,159'Single layer polysilicon EEPROM having uniform thickness gate oxide/capacitor dielectric layer'19955,340,764'Integration of high performance submicron CMOS and dual-poly non-volatile memory devices using a third polysilicon layer'1994Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1994–2000Patents assigned to ATMEL CORP (4)· patent assignee history
1994–2014Based in Colorado Springs, CO, US· patent location history
1998–1999Patents assigned to SYMBIOS INC (4)· patent assignee history
2000–2007Patents assigned to LSI LOGIC CORP (27)· patent assignee history
2001Based in Savage, MN, US· patent location history
2008–2014Patents assigned to LSI CORP (6)· patent assignee history
2011–2013Patents assigned to HONEYWELL INT INC (4)· patent assignee history
2011–2012Based in Mound, MN, US· patent location history
2011–2012Based in Plymouth, MN, US· patent location history
2013Based in Morristown, NJ, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| LSI LOGIC CORP | 27 | 2000–2007 |
| LSI CORP | 6 | 2008–2014 |
| ATMEL CORP | 4 | 1994–2000 |
| HONEYWELL INT INC | 4 | 2011–2013 |
| SYMBIOS INC | 4 | 1998–1999 |
Locations
| Location | Patents | Span |
|---|---|---|
| Colorado Springs, CO, US | 41 | 1994–2014 |
| Mound, Minnesota, US | 4 | 2011–2012 |
| Plymouth, Minnesota, US | 2 | 2011–2012 |
| Morristown, New Jersey, US | 1 | 2013 |
| Savage, Minnesota, US | 1 | 2001 |