Inventor
Cyril Cabral, Jr.
Inventor
Ossining, NY, US
Overview
Patents· 181 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices30%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1019%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%
H01LSemiconductor devices7%
C23CCoating metallic material4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation3%
H10BElectronic memory devices2%
C25DProcesses for the electrolytic or electrophoretic production of coatings1%
Y10TTechnical subjects covered by former us classification1%
PatentTitleYear
10,727,121Thin film interconnects with large grains202010,535,713Integrated reactive material erasure element with phase change memory202010,446,421Crystal oscillator and the use thereof in semiconductor fabrication201910,388,615Activating reactions in integrated circuits through electrical discharge201910,290,594Fragmenting computer chips201910,262,955Activating reactions in integrated circuits through electrical discharge201910,214,809Energy release using tunable reactive materials201910,170,361Thin film interconnects with large grains201910,043,765Damaging integrated circuit components20189,991,214Activating reactions in integrated circuits through electrical discharge20189,970,102Energy release using tunable reactive materials20189,971,341Crystal oscillator and the use thereof in semiconductor fabrication20189,941,004Integrated arming switch and arming switch activation layer for secure memory20189,859,227'Damaging integrated circuit components'20189,738,560'Controlling fragmentation of chemically strengthened glass'20179,691,656'Self-forming embedded diffusion barriers'20179,586,857'Controlling fragmentation of chemically strengthened glass'20179,490,202'Self-aligned airgap interconnect structures'20169,431,354'Activating reactions in integrated circuits through electrical discharge'20169,299,665'Formation of alpha particle shields in chip packaging'20169,299,639'Patterning transition metals in integrated circuits'20169,299,638'Patterning transition metals in integrated circuits'20169,263,393'Sputter and surface modification etch processing for metal patterning in integrated circuits'20169,190,321'Self-forming embedded diffusion barriers'20159,166,014'Gate electrode with stabilized metal semiconductor alloy-semiconductor stack'20159,064,727'Sputter and surface modification etch processing for metal patterning in integrated circuits'20159,034,749'Gate electrode with stabilized metal semiconductor alloy-semiconductor stack'20158,941,123'Local interconnects by metal-III-V alloy wiring in semi-insulating III-V substrates'20158,928,145'Formation of alpha particle shields in chip packaging'20158,900,988'Method for forming self-aligned airgap interconnect structures'20148,841,652'Self aligned carbide source/drain FET'20148,841,770'Semiconductor interconnect structure having enhanced performance and reliability'20148,836,048'Field effect transistor device having a hybrid metal gate stack'20148,828,870'Microstructure modification in copper interconnect structures'20148,772,161'Annealing copper interconnects'20148,658,461'Self aligned carbide source/drain FET'20148,648,465'Semiconductor interconnect structure having enhanced performance and reliability'20148,633,117'Sputter and surface modification etch processing for metal patterning in integrated circuits'20148,492,899'Method to electrodeposit nickel on silicon for forming controllable nickel silicide'20138,492,897'Microstructure modification in copper interconnect structures'20138,431,486'Interconnect structure for improved time dependent dielectric breakdown'20138,426,236'Method and structure of photovoltaic grid stacks by solution based processes'20138,362,600'Method and structure to reduce soft error rate susceptibility in semiconductor structures'20138,293,643'Method and structure of forming silicide and diffusion barrier layer with direct deposited film on silicon'20128,247,271'Formation of alpha particle shields in chip packaging'20128,212,218'Dosimeter powered by passive RF absorption'20128,193,051'Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics'20128,158,449'Particle emission analysis for semiconductor fabrication steps'20128,154,130'Self-aligned metal to form contacts to Ge containing substrates and structure formed thereby'20128,129,267'Alpha particle blocking wire structure and method fabricating same'20128,125,082'Reduction of silicide formation temperature on SiGe containing substrates'20128,101,518'Method and process for forming a self-aligned silicide contact'20128,089,157'Contact metallurgy structure'20128,039,331'Opto-thermal annealing methods for forming metal gate and fully silicided gate-field effect transistors'20118,008,199'Microstructure modification in copper interconnect structure'20117,998,842'Atomic layer deposition metallic contacts, gates and diffusion barriers'20117,928,514'Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics'20117,868,410'Gate stack engineering by electrochemical processing utilizing through-gate-dielectric current flow'20117,863,083'High temperature processing compatible metal gate electrode for pFETS and methods for fabrication'20117,851,357'Method of forming electrodeposited contacts'20107,843,063'Microstructure modification in copper interconnect structure'20107,804,391'Changing an electrical resistance of a resistor'20107,785,999'Formation of fully silicided metal gate using dual self-aligned silicide process'20107,781,871'Structure for reduction of soft error rates in integrated circuits'20107,749,847'CMOS integration scheme employing a silicide electrode and a silicide-germanide alloy electrode'20107,749,898'Silicide interconnect structure'20107,745,278'Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high K dielectrics'20107,682,968'Self-aligned metal to form contacts to Ge containing substrates and structure formed thereby'20107,667,278'Metal carbide gate structure and method of fabrication'20107,655,557'CMOS silicide metal gate integration'20107,601,627'Method for reduction of soft error rates in integrated circuits'20097,566,938'Deposition of hafnium oxide and/or zirconium oxide and fabrication of passivated electronic structures'20097,544,610'Method and process for forming a self-aligned silicide contact'20097,498,640'Self-aligned silicide process for silicon sidewall source and drain contacts and structure formed thereby'20097,479,683'Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics'20097,452,767'Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectrics'20087,449,782'Self-aligned metal to form contacts to Ge containing substrates and structure formed thereby'20087,410,852'Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors'20087,411,227'CMOS silicide metal gate integration'20087,405,154'Structure and method of forming electrodeposited contacts'20087,384,868'Reduction of silicide formation temperature on SiGe containing substrates'20087,381,635'Method and structure for reduction of soft error rates in integrated circuits'20087,378,338'Method of forming an interconnect structure diffusion barrier with high nitrogen content'20087,368,045'Gate stack engineering by electrochemical processing utilizing through-gate-dielectric current flow'20087,326,610'Process options of forming silicided metal gates for advanced CMOS devices'20087,314,789'Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification'20087,282,403'Temperature stable metal nitride gate electrode'20077,271,455'Formation of fully silicided metal gate using dual self-aligned silicide process'20077,271,699'Changing an electrical resistance of a resistor'20077,271,486'Retarding agglomeration of Ni monosilicide using Ni alloys'20077,242,055'Nitrogen-containing field effect transistor gate stack containing a threshold voltage control layer formed via deposition of a metal oxide'20077,223,691'Method of forming low resistance and reliable via in inter-level dielectric interconnect'20077,217,655'Electroplated CoWP composite structures as copper barrier layers'20077,193,323'Electroplated CoWP composite structures as copper barrier layers'20077,183,182'Method and apparatus for fabricating CMOS field effect transistors'20077,176,116'High performance FET with laterally thin extension'20077,173,312'Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification'20077,151,023'Metal gate MOSFET by full semiconductor metal alloy conversion'20067,122,472'Method for forming self-aligned dual fully silicided gates in CMOS devices'20067,112,481'Method for forming self-aligned dual salicide in CMOS technologies'20067,112,851'Field effect transistor with electroplated metal gate'20067,105,889'Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectrics'20067,102,234'Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloy'20067,098,537'Interconnect structure diffusion barrier with high nitrogen content'20067,081,676'Structure for controlling the interface roughness of cobalt disilicide'20067,074,684'Elevated source drain disposable spacer CMOS'20067,067,368'Method for forming self-aligned dual salicide in CMOS technologies'20067,064,050'Metal carbide gate structure and method of fabrication'20067,064,025'Method for forming self-aligned dual salicide in CMOS technologies'20067,056,782'CMOS silicide metal gate integration'20067,029,966'Process options of forming silicided metal gates for advanced CMOS devices'20067,023,064'Temperature stable metal nitride gate electrode'20066,989,322'Method of forming ultra-thin silicidation-stop extensions in mosfet devices'20066,987,050'Self-aligned silicide (salicide) process for low resistivity contacts to thin film silicon-on-insulator and bulk MOSFETS and for shallow junctions'20066,982,230'Deposition of hafnium oxide and/or zirconium oxide and fabrication of passivated electronic structures'20066,979,393'Method for plating copper conductors and devices formed'20056,972,250'Method and structure for ultra-low contact resistance CMOS formed by vertically self-aligned CoSi2 on raised source drain Si/SiGe device'20056,967,131'Field effect transistor with electroplated metal gate'20056,943,097'Atomic layer deposition of metallic contacts, gates and diffusion barriers'20056,933,577'High performance FET with laterally thin extension'20056,927,117'Method for integration of silicide contacts and silicide gate metals'20056,921,711'Method for forming metal replacement gate of high performance'20056,909,145'Metal spacer gate for CMOS FET'20056,905,560'Retarding agglomeration of Ni monosilicide using Ni alloys'20056,878,624'Pre-anneal of CoSi, to prevent formation of amorphous layer between Ti-O-N and CoSi'20056,862,799'Method for changing an electrical resistance of a resistor'20056,846,734'Method and process to make multiple-threshold metal gates CMOS technology'20056,831,369'Semiconductor structure having in-situ formed unit resistors and method for fabrication'20046,828,232'Semiconductor structure having in-situ formed unit resistors and method for fabrication'20046,809,030'Method and structure for controlling the interface roughness of cobalt disilicide'20046,794,226'Semiconductor device incorporating elements formed of refractory metal-silicon-nitrogen and method for fabrication'20046,777,298'Elevated source drain disposable spacer CMOS'20046,773,982'Feram cell with internal oxygen source and method of oxygen release'20046,753,606'Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloy'20046,716,708'Self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed thereby'20046,707,097'Method for forming refractory metal-silicon-nitrogen capacitors and structures formed'20046,700,203'Semiconductor structure having in-situ formed unit resistors'20046,690,072'Method and structure for ultra-low contact resistance CMOS formed by vertically self-aligned CoSi2 on raised source drain Si/SiGe device'20046,647,614'Method for changing an electrical resistance of a resistor'20036,645,861'Self-aligned silicide process for silicon sidewall source and drain contacts'20036,589,874'Method for forming electromigration-resistant structures by doping'20036,570,255'Method for forming interconnects on semiconductor substrates and structures formed'20036,555,880'Self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed thereby'20036,545,339'Semiconductor device incorporating elements formed of refractory metal-silicon-nitrogen and method for fabrication'20036,524,908'Method for forming refractory metal-silicon-nitrogen capacitors and structures formed'20036,503,833'Self-aligned silicide (salicide) process for strained silicon MOSFET ON SiGe and structure formed thereby'20036,503,641'Interconnects with Ti-containing liners'20036,448,131'Method for increasing the capacitance of a trench capacitor'20026,444,578'Self-aligned silicide process for reduction of Si consumption in shallow junction and thin SOI electronic devices'20026,440,851'Method and structure for controlling the interface roughness of cobalt disilicide'20026,437,440'Thin film metal barrier for electrical interconnections'20026,436,823'Method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure and structure formed'20026,429,523'Method for forming interconnects on semiconductor substrates and structures formed'20026,413,859'Method and structure for retarding high temperature agglomeration of silicides using alloys'20026,391,773'Method and materials for through-mask electroplating and selective base removal'20026,388,285'Feram cell with internal oxygen source and method of oxygen release'20026,388,327'Capping layer for improved silicide formation in narrow semiconductor structures'20026,380,075'Method for forming an open-bottom liner for a conductor in an electronic structure and device formed'20026,344,129'Method for plating copper conductors and devices formed'20026,331,486'Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloy'20016,323,130'Method for self-aligned formation of silicide contacts using metal silicon alloys for limited silicon consumption and for reduction of bridging'20016,291,885'Thin metal barrier for electrical interconnections'20016,268,291'Method for forming electromigration-resistant structures by doping'20016,187,679'Low temperature formation of low resistivity titanium silicide'20016,188,120'Method and materials for through-mask electroplating and selective base removal'20015,945,737'Thin film or solder ball including a metal and an oxide, nitride, or carbide precipitate of an expandable or contractible element'19995,834,374'Method for controlling tensile and compressive stresses and mechanical problems in thin films on substrates'19985,828,131'Low temperature formation of low resistivity titanium silicide'19985,796,166'Tasin oxygen diffusion barrier in multilayer structures'19985,776,823'Tasin oxygen diffusion barrier in multilayer structures'19985,639,316'Thin film multi-layer oxygen diffusion barrier consisting of aluminum on refractory metal'19975,634,973'Low temperature selective growth of silicon or silicon alloys'19975,624,869'Method of forming a film for a multilayer Semiconductor device for improving thermal stability of cobalt silicide using platinum or nitrogen'19975,625,233'Thin film multi-layer oxygen diffusion barrier consisting of refractory metal, refractory metal aluminide, and aluminum oxide'19975,608,266'Thin film for a multilayer semiconductor device for improving thermal stability and a method thereof'19975,595,600'Low temperature selective growth of silicon or silicon alloys'19975,576,579'Tasin oxygen diffusion barrier in multilayer structures'19965,565,031'Method for low temperature selective growth of silicon or silicon alloys'19965,510,295'Method for lowering the phase transformation temperature of a metal silicide'19965,427,630'Mask material for low temperature selective growth of silicon or silicon alloys'19955,401,677'Method of metal silicide formation in integrated circuit devices'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995–2020Patents assigned to IBM (173)· patent assignee history
1995–2012Based in Ossining, NY, US· patent location history
2006–2020Based in Mahopac, NY, US· patent location history
2010–2019Patents assigned to GLOBALFOUNDRIES INC (9)· patent assignee history
2010–2019Based in Yorktown Heights, NY, US· patent location history
2012–2015Patents assigned to CABRAL JR CYRIL (21)· patent assignee history
2012–2014Patents assigned to LAVOIE CHRISTIAN (8)· patent assignee history
2012–2015Patents assigned to RODBELL KENNETH P (7)· patent assignee history
2018Based in Mahaopac, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 173 | 1995–2020 |
| CABRAL JR CYRILself | 21 | 2012–2015 |
| GLOBALFOUNDRIES INC | 9 | 2010–2019 |
| LAVOIE CHRISTIAN | 8 | 2012–2014 |
| RODBELL KENNETH P | 7 | 2012–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Ossining, New York, US | 96 | 1995–2012 |
| Mahopac, New York, US | 75 | 2006–2020 |
| Yorktown Heights, New York, US | 9 | 2010–2019 |
| Mahaopac, New York, US | 1 | 2018 |