Inventor
Da-Yuan Shih
Inventor
Poughkeepsie, NY, US
Overview
Patents· 116 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1027%
Y10TTechnical subjects covered by former us classification13%
H05KPrinted circuits11%
G01RMeasuring electric variables11%
H01LSemiconductor devices8%
B23KSoldering or unsoldering5%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h103%
H01RElectrically-conductive connections2%
Y02PClimate change mitigation technologies in the production or processing of goods2%
PatentTitleYear
11,110,534Continuous solder transfer to substrates202110,833,120Injection molded microoptics202010,490,594Injection molded microoptics201910,340,226Interconnect crack arrestor structure and methods201910,034,390Metal post bonding using pre-fabricated metal posts20189,978,709Solder bump stretching method for forming a solder bump joint in a device20189,679,875'Reduced volume interconnect for three-dimensional chip stack'20179,679,882'Method of multi-chip wafer level packaging'20179,543,273'Reduced volume interconnect for three-dimensional chip stack'20179,521,795'Two-step direct bonding processes and tools for performing the same'20169,490,408'Injection molded microoptics'20169,475,145'Solder bump joint in a device including lamellar structures'20169,404,942'Coaxial probe structure of elongated electrical conductors projecting from a support structure'20169,343,423'No flow underfill or wafer level underfill and solder columns'20169,305,896'No flow underfill or wafer level underfill and solder columns'20169,263,407'Method for manufacturing a plurality of metal posts'20169,252,120'Copper post solder bumps on substrates'20169,230,932'Interconnect crack arrestor structure and methods'20169,216,469'Indirect printing bumping method for solder ball deposition'20159,082,762'Electromigration-resistant under-bump metallization of nickel-iron alloys for Sn-rich solder bumps in Pb-free flip-clip'20159,082,763'Joint structure for substrates and methods of forming'20159,012,266'Copper post solder bumps on substrates'20158,963,340'No flow underfill or wafer level underfill and solder columns'20158,945,995'Copper post solder bumps on substrates'20158,927,877'Looped interconnect structure'20158,877,556'Copper post solder bumps on substrates'20148,803,333'Three-dimensional chip stack and method of forming the same'20148,754,666'Probe structure having a plurality of discrete insulated probe tips projecting from a support surface, apparatus for use thereof and methods of fabrication thereof'20148,754,514'Multi-chip wafer level package'20148,703,274'Microcavity structure and process'20148,691,685'Prevention and control of intermetallic alloy inclusions that form during reflow of Pb free, Sn rich, solders in contacts in microelectronic packaging in integrated circuit contact structures where electroless Ni(P) metallization is present'20148,685,798'Methods for forming through vias'20148,679,964'Prevention and control of intermetallic alloy inclusions'20148,669,137'Copper post solder bumps on substrate'20148,541,299'Electrical interconnect forming method'20138,491,772'Redox method of forming a coaxial probe structure of elongated electrical conductors projecting from a support structure'20138,486,250'Electrodeposition method of forming a probe structure having a plurality of discrete insulated probe tips projecting from a support surface'20138,476,770'Apparatus and methods for forming through vias'20138,476,773'Electrical interconnect structure'20138,314,500'Interconnections for flip-chip using lead-free solders and having improved reaction barrier layers'20128,268,719'Sprocket opening alignment process and apparatus for multilayer solder decal'20128,242,010'Electrical interconnect forming method'20128,156,998'Patterned metal thermal interface'20128,157,158'Modification of solder alloy compositions to suppress interfacial void formation in solder joints'20128,039,314'Metal adhesion by induced surface roughness'20118,026,613'Interconnections for flip-chip using lead-free solders and having reaction barrier layers'20118,003,512'Structure of UBM and solder bumps and methods of fabrication'20117,978,473'Cooling apparatus with cold plate formed in situ on a surface to be cooled'20117,932,169'Interconnection for flip-chip using lead-free solders and having improved reaction barrier layers'20117,928,585'Sprocket opening alignment process and apparatus for multilayer solder decal'20117,923,849'Interconnections for flip-chip using lead-free solders and having reaction barrier layers'20117,898,076'Structure and methods of processing for solder thermal interface materials for chip cooling'20117,838,954'Semiconductor structure with solder bumps'20107,819,376'Techniques for forming interconnects'20107,786,001'Electrical interconnect structure and method'20107,784,669'Method and process for reducing undercooling in a lead-free tin-rich solder alloy'20107,731,079'Cooling apparatus and method of fabrication thereof with a cold plate formed in situ on a surface to be cooled'20107,703,661'Method and process for reducing undercooling in a lead-free tin-rich solder alloy'20107,694,719'Patterned metal thermal interface'20107,538,565'High density integrated circuit apparatus, test probe and methods of use thereof'20097,523,852'Solder interconnect structure and method using injection molded solder'20097,495,342'Angled flying lead wire bonding process'20097,410,833'Interconnections for flip-chip using lead-free solders and having reaction barrier layers'20087,399,421'Injection molded microoptics'20087,368,924'Probe structure having a plurality of discrete insulated probe tips projecting from a support surface, apparatus for use thereof and methods of fabrication thereof'20087,348,270'Techniques for forming interconnects'20087,332,922'Method for fabricating a structure for making contact with a device'20087,282,945'Wafer scale high density probe assembly, apparatus for use thereof and methods of fabrication thereof'20077,276,919'High density integral test probe'20077,273,803'Ball limiting metallurgy, interconnection structure including the same, and method of forming an interconnection structure'20077,180,179'Thermal interposer for thermal management of semiconductor devices'20077,079,393'Fluidic cooling systems and methods for electronic components'20067,002,247'Thermal interposer for thermal management of semiconductor devices'20066,891,360'Plated probe structure'20056,880,245'Method for fabricating a structure for making contact with an IC device'20056,805,974'Lead-free tin-silver-copper alloy solder composition'20046,722,032'Method of forming a structure for electronic devices contact locations'20046,708,403'Angled flying lead wire bonding process'20046,528,984'Integrated compliant probe for wafer level test and burn-in'20036,526,655'Angled flying lead wire bonding process'20036,525,551'Probe structures for testing electrical interconnections to integrated circuit electronic devices'20036,523,255'Process and structure to repair damaged probes mounted on a space transformer'20036,451,155'Method using a thin adhesion promoting layer for bonding silicone elastomeric material to nickel and use thereof in making a heat sink assembly'20026,452,406'Probe structure having a plurality of discrete insulated probe tips'20026,334,247'High density integrated circuit apparatus, test probe and methods of use thereof'20026,332,270'Method of making high density integral test probe'20016,329,827'High density cantilevered probe for electronic devices'20016,300,780'High density integrated circuit apparatus, test probe and methods of use thereof'20016,295,729'Angled flying lead wire bonding process'20016,286,208'Interconnector with contact pads having enhanced durability'20016,206,273'Structures and processes to create a desired probetip contact geometry on a wafer test probe'20016,104,201'Method and apparatus for passive characterization of semiconductor substrates subjected to high energy (MEV) ion implementation using high-injection surface photovoltage'20006,078,500'Pluggable chip scale package'20006,062,879'High density test probe with rigid surface structure'20006,054,651'Foamed elastomers for wafer probing applications and interposer connectors'20005,931,222'Adhesion promoting layer for bonding polymeric adhesive to metal and a heat sink assembly using same'19995,914,614'High density cantilevered probe for electronic devices'19995,838,160'Integral rigid chip test probe'19985,821,763'Test probe for high density integrated circuits, methods of fabrication thereof and methods of use thereof'19985,810,607'Interconnector with contact pads having enhanced durability'19985,804,607'Process for making a foamed elastomeric polymer'19985,785,538'High density test probe with rigid surface structure'19985,756,021'Electronic devices comprising dielectric foamed polymers'19985,726,211'Process for making a foamed elastometric polymer'19985,700,844'Process for making a foamed polymer'19975,635,846'Test probe having elongated conductor embedded in an elostomeric material which is mounted on a space transformer'19975,531,022'Method of forming a three dimensional high performance interconnection package'19965,441,690'Process of making pinless connector'19955,433,631'Flex circuit card elastomeric cable connector assembly'19955,386,344'Flex circuit card elastomeric cable connector assembly'19955,371,654'Three dimensional high performance interconnection package'19944,970,570'Use of tapered head pin design to improve the stress distribution in the braze joint'19904,880,684'Sealing and stress relief layers and use thereof'19894,835,593'Multilayer thin film metallurgy for pin brazing'19894,781,970'Strengthening a ceramic by post sinter coating with a compressive surface layer'19884,751,349'Zirconium as an adhesion material in a multi-layer metallic structure'1988Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1988–2021Patents assigned to IBM (98)· patent assignee history
1988–2021Based in Poughkeepsie, NY, US· patent location history
2012–2016Patents assigned to SHIH DA-YUAN (22)· patent assignee history
2012–2016Patents assigned to NAH JAE-WOONG (7)· patent assignee history
2013–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (8)· patent assignee history
2013–2019Based in Hsinchu, TW· patent location history
2014–2016Based in Armonk, NY, US· patent location history
2015–2019Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (7)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 98 | 1988–2021 |
| SHIH DA-YUANself | 22 | 2012–2016 |
| TAIWAN SEMICONDUCTOR MFG | 8 | 2013–2016 |
| NAH JAE-WOONG | 7 | 2012–2016 |
| TAIWAN SEMICONDUCTOR MFG CO LTD | 7 | 2015–2019 |
Locations
| Location | Patents | Span |
|---|---|---|
| Poughkeepsie, New York, US | 92 | 1988–2021 |
| Hsinchu, TW | 15 | 2013–2019 |
| Armonk, New York, US | 9 | 2014–2016 |