Inventor
Michael D. Steigerwalt
Inventor
Newburgh, NY, US
Overview
Patents· 16 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices44%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1030%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1015%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests7%
H10BElectronic memory devices4%
PatentTitleYear
8,598,009'Self-aligned embedded SiGe structure and method of manufacturing the same'20138,232,186'Methods of integrating reverse eSiGe on NFET and SiGe channel on PFET, and related structure'20128,222,673'Self-aligned embedded SiGe structure and method of manufacturing the same'20127,911,024'Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof'20117,763,518'Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof'20107,691,716'Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation'20107,485,537'Method of fabricating a vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness'20097,394,131'STI formation in semiconductor device including SOI and bulk silicon regions'20087,375,410'Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof'20087,118,986'STI formation in semiconductor device including SOI and bulk silicon regions'20067,115,463'Patterning SOI with silicon mask to create box at different depths'20067,115,965'Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation'20066,995,094'Method for deep trench etching through a buried insulator layer'20066,964,897'SOI trench capacitor cell incorporating a low-leakage floating body array transistor'20056,900,092'Surface engineering to prevent epi growth on gate poly during selective epi processing'20056,440,807'Surface engineering to prevent EPI growth on gate poly during selective EPI processing'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2013Patents assigned to IBM (16)· patent assignee history
2002–2013Based in Newburgh, NY, US· patent location history
2012–2013Patents assigned to HOLT JUDSON R (3)· patent assignee history
2012–2013Patents assigned to STEIGERWALT MICHAEL D (3)· patent assignee history
2012–2013Patents assigned to AMARNATH KULDEEP (2)· patent assignee history
2012–2013Patents assigned to GLOBALFOUNDRIES INC (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 16 | 2002–2013 |
| HOLT JUDSON R | 3 | 2012–2013 |
| STEIGERWALT MICHAEL Dself | 3 | 2012–2013 |
| AMARNATH KULDEEP | 2 | 2012–2013 |
| GLOBALFOUNDRIES INC | 2 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Newburgh, New York, US | 16 | 2002–2013 |