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Inventor

Michael Altmann

Inventor
Folsom, CA, US

Overview

26→
Patents
1993–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 26 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H03Lprimary
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses22%
H04LTransmission of digital information, e.g. telegraphic communication22%
H04JMultiplex communication9%
H03KPulse technique7%
H10DInorganic electric semiconductor devices7%
H03FAmplifiers4%
H03HImpedance networks, e.g. resonant circuits4%
B29CShaping or joining of plastics2%
C07KPeptides2%
C12NMicroorganisms or enzymes2%
PatentTitleYear
10,615,893Transmitter with feedback control202010,374,785Clock phase adjustment using clock and data recovery scheme20199,049,001'Apparatus, system, and method for timing recovery'20158,799,009'Systems, methods and apparatuses for predicting capacity of resources in an institution'20148,451,969'Apparatus, system, and method for timing recovery'20137,889,824'System and method for alignment of clock to data'20117,885,368'Analog phase controller'20117,706,392'Dynamic power management in a power over ethernet system'20107,498,889'Analog phase controller'20097,368,955'Current-balanced logic circuit'20087,203,259'Phase interpolator'20077,197,101'Phase interpolator based clock recovering'20076,855,995'Physically defined varactor in a CMOS process'20056,849,488'Physically defined varactor in a CMOS process'20056,764,891'Physically defined varactor in a CMOS process'20046,748,027'CMI signal timing recovery'20046,448,848'Method of controlling common-mode in differential gm-C circuits'20026,424,230'Loop stabilization technique in a phase locked loop (PLL) with amplitude compensation'20025,945,860'CLM/ECL clock phase shifter with CMOS digital control'19995,844,436'Method of recovering a sampling clock in a framed data communications format with reduced phase jitter and wander'19985,825,825'Method of processing multi-level signals for simple clock recovery'19985,708,391'High frequency differential filter with CMOS control'19985,554,901'Servo-drive for rotary angle adjustment of an actuator for controlling an opening cross-section of a medium flow line'19965,420,529'Current steering switch and hybrid BiCMOS multiplexer with CMOS commutation signal and CML/ECL data signals'19955,415,714'Method for positionally securing two different components together'19955,219,989'Bifunctional protein for the isolation of capped mRNA'1993

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1995–1999Patents assigned to NORTHERN TELECOM LTD (4)· patent assignee history
1995–1996Patents assigned to BOSCH GMBH ROBERT (2)· patent assignee history
1995–1999Based in Kanata, CA· patent location history
1995–1996Based in Loechgau, DE· patent location history
1998Based in Sacramento, CA, US· patent location history
2002–2020Patents assigned to INTEL CORP (16)· patent assignee history
2002–2020Based in Folsom, CA, US· patent location history
2013–2015Patents assigned to ALTMANN MICHAEL W (2)· patent assignee history
2013–2015Patents assigned to JIANG YUEMING (2)· patent assignee history
2014Based in Minneapolis, MN, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
INTEL CORP162002–2020
NORTHERN TELECOM LTD41995–1999
ALTMANN MICHAEL Wself22013–2015
BOSCH GMBH ROBERT21995–1996
JIANG YUEMING22013–2015
Locations
LocationPatentsSpan
Folsom, California, US172002–2020
Kanata, CA31995–1999
Sacramento, California, US21998
Loechgau, DE21995–1996
Minneapolis, Minnesota, US12014