Inventor
Raymond Leung
Inventor
Palo Alto, CA, US
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores26%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes12%
A63FCard, board, or roulette games9%
A45CPurses6%
B29CShaping or joining of plastics6%
B29KIndexing scheme associated with subclasses b29b, b29c or b29d, relating to moulding materials or to materials for moulds, reinforcements, fillers or preformed parts, e.g. inserts6%
B29LIndexing scheme associated with subclass b29c, relating to particular articles6%
G01RMeasuring electric variables6%
G06FElectric digital data processing6%
H04BTransmission6%
PatentTitleYear
10,868,996Protective covering for an electronic device202010,763,911Protective covering for an electronic device202010,192,260Tool for generating containerized processing logic for use in insurance claim processing20199,914,050'Guitar shaped video game controller'20189,908,042'Guitar shaped video game controller'20189,908,043'Guitar shaped video game controller'20189,857,409'Negative bias thermal instability stress testing of transistors'20189,817,059'Evaluation of thermal instability stress testing'20179,742,406'Circuit skew compensation trigger system'20179,424,951'Dynamic static random access memory (SRAM) array characterization using an isolated bit-line'20168,825,504'Modifying containerized processing logic for use in insurance claim processing'20148,706,532'Insurance claim processing using containerized processing logic'20148,355,930'Insurance claim processing using containerized processing logic'20137,734,999'System and method for providing forms on a user interface'20105,982,659'Memory cell capable of storing more than two logic states by using different via resistances'19995,867,423'Memory circuit and method for multivalued logic storage by process variations'19995,847,990'Ram cell capable of storing 3 logic states'19985,808,932'Memory system which enables storage and retrieval of more than two states in a memory cell'19985,784,328'Memory system including an on-chip temperature sensor for regulating the refresh rate of a DRAM array'19985,761,110'Memory cell capable of storing more than two logic states by using programmable resistances'19985,045,726'Low power programming circuit for user programmable digital logic array'1991Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1991–2018Based in Palo Alto, CA, US· patent location history
1998–1999Patents assigned to LSI LOGIC CORP (6)· patent assignee history
2010–2014Patents assigned to EMERGIS INC (4)· patent assignee history
2010–2019Based in Calgary, CA· patent location history
2013–2019Patents assigned to LEUNG RAYMOND (3)· patent assignee history
2016–2018Patents assigned to SYNOPSYS INC (4)· patent assignee history
2018Patents assigned to PERFORMANCE DESIGNED PRODUCTS LLC (3)· patent assignee history
2018Based in Burbank, CA, US· patent location history
2020Based in Chai Wan, HK· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| LSI LOGIC CORP | 6 | 1998–1999 |
| EMERGIS INC | 4 | 2010–2014 |
| SYNOPSYS INC | 4 | 2016–2018 |
| LEUNG RAYMONDself | 3 | 2013–2019 |
| PERFORMANCE DESIGNED PRODUCTS LLC | 3 | 2018 |
Locations
| Location | Patents | Span |
|---|---|---|
| Palo Alto, California, US | 11 | 1991–2018 |
| Calgary, CA | 5 | 2010–2019 |
| Burbank, California, US | 3 | 2018 |
| Chai Wan, HK | 2 | 2020 |