Inventor
Brian D. McMinn
Inventor
Buda, TX, US
Overview
Patents· 37 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing69%
G11CStatic stores7%
H04LTransmission of digital information, e.g. telegraphic communication7%
G01RMeasuring electric variables4%
H03KPulse technique4%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use4%
G11BInformation storage based on relative movement between record carrier and transducer2%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses2%
PatentTitleYear
8,010,920'Constraint management and validation for template-based circuit design'20117,937,569'System and method for scheduling operations using speculative data operands'20117,827,355'Data processor having a cache with efficient storage of predecode information, cache, and method'20107,315,935'Apparatus and method for port arbitration in a register file on the basis of functional unit issue slots'20087,133,969'System and method for handling exceptional instructions in a trace cache based processor'20067,127,573'Memory controller providing multiple power modes for accessing memory devices by reordering memory transactions'20067,080,170'Circular buffer using age vectors'20067,069,411'Mapper circuit with backup capability'20067,043,626'Retaining flag value associated with dead result data in freed rename physical register with an indicator to select set-aside register instead for renaming'20066,957,319'Integrated circuit with multiple microcode ROMs'20056,873,184'Circular buffer using grouping for find first function'20056,782,486'Apparatus for stopping and starting a clock in a clock forwarded I/O system depending on the presence of valid data in a receive buffer'20046,760,392'Method and apparatus to provide fixed latency early response in a system with multiple clock domains with fixable clock ratios'20046,711,696'Method for transfering data between two different clock domains by calculating which pulses of the faster clock domain should be skipped substantially simultaneously with the transfer'20046,597,620'Storage circuit with data retention during power down'20036,539,470'Instruction decode unit producing instruction operand information in the order in which the operands are identified, and systems including same'20036,424,688'Method to transfer data in a system with multiple clock domains using clock skipping techniques'20026,298,424'Computer system including priorities for memory operations and allowing a higher priority memory operation to interrupt a lower priority memory operation'20016,219,760'Cache including a prefetch way for storing cache lines and configured to move a prefetched cache line to a non-prefetch way upon access to the prefetched cache line'20016,151,662'Data transaction typing for improved caching and prefetching characteristics'20006,138,213'Cache including a prefetch way for storing prefetch cache lines and configured to move a prefetched cache line to a non-prefetch way upon access to the prefetched cache line'20006,097,403'Memory including logic for operating upon graphics primitives'20006,058,461'Computer system including priorities for memory operations and allowing a higher priority memory operation to interrupt a lower priority memory operation'20006,032,252'Apparatus and method for efficient loop control in a superscalar microprocessor'20005,926,646'Context-dependent memory-mapped registers for transparent expansion of a register file'19995,727,177'Reorder buffer circuit accommodating special instructions operating on odd-width results'19985,721,695'Simulation by emulating level sensitive latches with edge trigger latches'19985,646,893'Segmented read line circuit particularly useful for multi-port storage arrays'19975,570,294'Circuit configuration employing a compare unit for testing variably controlled delay units'19965,430,394'Configuration and method for testing a delay chain within a microprocessor clock generator'19955,327,571'Processor having decoder for decoding unmodified instruction set for addressing register to read or write in parallel or serially shift in from left or right'19945,267,186'Normalizing pipelined floating point processing unit'19935,077,692'Information storage device with batch select capability'19915,059,818'Self-regulating clock generator'19915,058,048'Normalizing pipelined floating point processing unit'19915,053,631'Pipelined floating point processing unit'19914,731,737'High speed intelligent distributed control memory system'1988Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1988–2011Patents assigned to ADVANCED MICRO DEVICES INC (36)· patent assignee history
1988–1994Based in Austin, TX, US· patent location history
1995–2011Based in Buda, TX, US· patent location history
2010Patents assigned to GLOBALFOUNDRIES INC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADVANCED MICRO DEVICES INC | 36 | 1988–2011 |
| GLOBALFOUNDRIES INC | 1 | 2010 |
Locations
| Location | Patents | Span |
|---|---|---|
| Buda, Texas, US | 30 | 1995–2011 |
| Austin, Texas, US | 7 | 1988–1994 |