Inventor

Tetsuo Gocho

Inventor

Kanagawa, JP

Overview

15→

Patents

1993–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 15 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1027%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1022%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests17%

H10DInorganic electric semiconductor devices12%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices10%

C23CCoating metallic material2%

H01JElectric discharge tubes or discharge lamps2%

H01LSemiconductor devices2%

H10BElectronic memory devices2%

H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation2%

PatentTitleYear

10,991,723Semiconductor device, method of manufacturing semiconductor device, and electronic apparatus2021 RE038363'Method of forming trench isolation having polishing step and method of manufacturing semiconductor device'2003 6,258,654'Method of manufacturing a semiconductor device'2001 6,218,266'Method of fabricating electronic devices of the type including smoothing process using polishing'2001 5,700,349'Method for forming multi-layer interconnections'1997 5,698,352'Semiconductor device containing Si, O and N anti-reflective layer'1997 5,648,202'Method of forming a photoresist pattern using an anti-reflective'1997 5,641,607'Anti-reflective layer used to form a semiconductor device'1997 5,632,910'Multilayer resist pattern forming method'1997 5,600,165'Semiconductor device with antireflection film'1997 5,502,008'Method for forming metal plug and/or wiring metal layer'1996 5,498,565'Method of forming trench isolation having polishing step and method of manufacturing semiconductor device'1996 5,472,827'Method of forming a resist pattern using an anti-reflective layer'1995 5,254,171'Bias ECR plasma CVD apparatus comprising susceptor, clamp, and chamber wall heating and cooling means'1993 5,242,853'Manufacturing process for a semiconductor device using bias ECRCVD and an etch stop layer'1993

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1993–2003Patents assigned to SONY CORP (14)· patent assignee history

1993–2021Based in Kanagawa, JP· patent location history

2001Based in Kanawaga, JP· patent location history

2021Patents assigned to SONY SEMICONDUCTOR SOLUTIONS CORP (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
SONY CORP	14	1993–2003
SONY SEMICONDUCTOR SOLUTIONS CORP	1	2021

Locations

Location	Patents	Span
Kanagawa, JP	14	1993–2021
Kanawaga, JP	1	2001