Inventor
RAGHUVEER REDDY PATLOLLA
Inventor
US
Overview
Patents· 4 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices36%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1036%
H10BElectronic memory devices9%
H10DInorganic electric semiconductor devices9%
H10NElectric solid-state devices not otherwise provided for9%
PatentTitleYear
12,107,008Maskless alignment scheme for BEOL memory array manufacturing202411,664,271Dual damascene with short liner202311,637,036Planarization stop region for use with low pattern density interconnects202311,164,878Interconnect and memory structures having reduced topography variation formed in the BEOL2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2024Patents assigned to IBM (4)· patent assignee history
2021–2024Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 4 | 2021–2024 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 4 | 2021–2024 |