Inventor
Tomonori Okudaira
Inventor
Hyogo, JP
Overview
Patents· 39 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices33%
H10BElectronic memory devices30%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests7%
C23CCoating metallic material5%
H01LSemiconductor devices2%
H03BGeneration of oscillations, directly or by frequency-changing, by circuits employing active elements which operate in a non-switching manner2%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses2%
PatentTitleYear
9,503,018'Semiconductor device'20169,252,793'Semiconductor device'20168,338,247'Semiconductor device and method of manufacturing same'20128,148,248'Semiconductor device and manufacturing method thereof'20128,022,445'Method of manufacturing a semiconductor device'20117,936,016'Semiconductor device and manufacturing method thereof'20117,872,314'Method of manufacturing semiconductor device carrying out ion implantation before silicide process'20117,696,050'Method of manufacturing semiconductor device carrying out ion implantation before silicide process'20107,517,800'Semiconductor device and manufacturing method thereof'20096,764,896'Semiconductor manufacturing method including patterning a capacitor lower electrode by chemical etching'20046,746,876'Capacitor manufacturing method having dielectric formed before electrode'20046,506,613'Method for manufacturing semiconductor device having a capacitor'20036,407,419'Semiconductor device and manufacturing method thereof'20026,278,150'Conductive layer connecting structure and method of manufacturing the same'20016,096,133'Chemical vapor deposition apparatus'20006,078,072'Semiconductor device having a capacitor'20006,033,732'Apparatus for and method of forming thin film by chemical vapor deposition'20005,972,748'Semiconductor memory device and method of manufacturing the same'19995,776,254'Apparatus for forming thin film by chemical vapor deposition'19985,753,527'Method of manufacturing a semiconductor memory device'19985,672,533'Field effect transistor having impurity regions of different depths and manufacturing method thereof'19975,668,041'Method of manufacturing a semiconductor device having a capacitor'19975,652,186'Semiconductor device and a method of manufacturing thereof'19975,572,052'Electronic device using zirconate titanate and barium titanate ferroelectrics in insulating layer'19965,534,458'Method of manufacturing a semiconductor device with high dielectric capacitor having sidewall spacers'19965,519,237'Semiconductor memory device'19965,489,791'Field effect transistor having impurity regions of different depths and manufacturing method thereof'19965,459,345'Semiconductor device high dielectric capacitor with narrow contact hole'19955,453,952'Semiconductor device having peripheral circuit formed of TFT (thin film transistor)'19955,442,213'Semiconductor device with high dielectric capacitor having sidewall spacers'19955,428,239'Semiconductor device having retrograde well and diffusion-type well'19955,418,388'Semiconductor device having a capacitor with an adhesion layer'19955,404,042'Semiconductor memory device having a plurality of well regions of different conductivities'19955,364,811'Method of manufacturing a semiconductor memory device with multiple device forming regions'19945,276,344'Field effect transistor having impurity regions of different depths and manufacturing method thereof'19945,229,314'Method of manufacturing field effect transistor having a multilayer interconnection layer therein with tapered sidewall insulation'19935,218,219'Semiconductor memory device having a peripheral wall at the boundary region of a memory cell array region and a peripheral circuit region'19935,164,806'Element isolating structure of semiconductor device suitable for high density integration'19925,157,469'Field effect transistor having a multilayer interconnection layer therein with tapered sidewall insulators'1992Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1992–2003Patents assigned to MITSUBISHI ELECTRIC CORP (27)· patent assignee history
1992–2009Based in Hyogo, JP· patent location history
1998–2012Based in Tokyo, JP· patent location history
2004–2010Patents assigned to RENESAS TECH CORP (4)· patent assignee history
2011–2016Patents assigned to RENESAS ELECTRONICS CORP (7)· patent assignee history
2012–2016Patents assigned to OKUDAIRA TOMONORI (3)· patent assignee history
2012–2016Patents assigned to TSUTSUMI TOSHIAKI (3)· patent assignee history
2016Based in Kanagawa, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MITSUBISHI ELECTRIC CORP | 27 | 1992–2003 |
| RENESAS ELECTRONICS CORP | 7 | 2011–2016 |
| RENESAS TECH CORP | 4 | 2004–2010 |
| OKUDAIRA TOMONORIself | 3 | 2012–2016 |
| TSUTSUMI TOSHIAKI | 3 | 2012–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hyogo, JP | 25 | 1992–2009 |
| Tokyo, JP | 12 | 1998–2012 |
| Kanagawa, JP | 2 | 2016 |