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Inventor

Koichi Magome

Inventor
Hiratsuka, JP

Overview

8→
Patents
1987–2013
Patent span
Physics
Primary field (CPC G)

Patents· 8 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores73%
H03KPulse technique18%
H04NPictorial communication, e.g. television9%
PatentTitleYear
8,488,391'Memory chip with buffer controlled based upon the last address cycle'20135,566,128'Semiconductor memory device'19965,497,352'Semiconductor memory device having dual mode operation'19965,319,603'Multiport semiconductor memory device having RAM blocks and SAM blocks'19945,168,468'Semiconductor memory device with column redundancy'19925,075,887'Semiconductor memory capable of improving data rewrite speed'19914,746,824'High potential hold circuit'19884,678,934'Flip-flop circuit'1987

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1987–2013Patents assigned to TOSHIBA KK (8)· patent assignee history
1987–1988Based in Yokohama, JP· patent location history
1991Based in Kawasaki, JP· patent location history
1992–1996Based in Hiratsuka, JP· patent location history
2013Patents assigned to MAGOME KOICHI (1)· patent assignee history
2013Patents assigned to MOCHIZUKI HIKARU (1)· patent assignee history
2013Patents assigned to NIINO YASUAKI (1)· patent assignee history
2013Based in Shanghai, CN· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TOSHIBA KK81987–2013
MAGOME KOICHIself12013
MOCHIZUKI HIKARU12013
NIINO YASUAKI12013
Locations
LocationPatentsSpan
Hiratsuka, JP41992–1996
Yokohama, JP21987–1988
Shanghai, CN12013
Kawasaki, JP11991