Inventor
Hsichang Liu
Inventor
Fishkill, NY, US
Overview
Patents· 18 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1022%
H05KPrinted circuits18%
Y10TTechnical subjects covered by former us classification17%
B32BLayered products, i.e. products built-up of strata of flat or non-flat, e.g. cellular or honeycomb, form5%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
B23KSoldering or unsoldering3%
B82YSpecific uses or applications of nanostructures3%
C22CAlloys3%
C23CCoating metallic material3%
C25DProcesses for the electrolytic or electrophoretic production of coatings3%
PatentTitleYear
8,910,853'Additives for grain fragmentation in Pb-free Sn-based solder'20148,493,746'Additives for grain fragmentation in Pb-free Sn-based solder'20138,232,636'Reliability enhancement of metal thermal interface'20128,156,990'Apparatus for providing uniaxial load distribution for laminate layers of multilayer ceramic chip carriers'20127,947,143'Method for providing uniaxial load distribution for laminate layers of multilayer ceramic chip carriers'20117,836,935'Apparatus for providing uniaxial load distribution for laminate layers of multilayer ceramic chip carriers'20107,683,493'Intermetallic diffusion block device and method of manufacture'20107,472,650'Nickel alloy plated structure'20097,369,410'Apparatuses for dissipating heat from semiconductor devices'20087,302,757'Micro-bumps to enhance LGA interconnections'20077,287,468'Nickel alloy plated structure'20077,078,320'Partial wafer bonding and dicing'20066,838,009'Rework method for finishing metallurgy on chip carriers'20056,662,718'Screening mask having a stress-relieving area'20036,348,233'Method of forming conductive line features for enhanced reliability of multi-layer ceramic substrates'20026,217,989'Conductive line features for enhanced reliability of multi-layer ceramic substrates'20015,985,128'Method of performing processes on features with electricity'19995,935,404'Method of performing processes on features with electricity'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2014Patents assigned to IBM (18)· patent assignee history
1999–2014Based in Fishkill, NY, US· patent location history
2012–2013Patents assigned to LIU HSICHANG (3)· patent assignee history
2012Patents assigned to NATARAJAN GOVINDARAJAN (2)· patent assignee history
2012–2013Patents assigned to WEISMAN RENEE L (2)· patent assignee history
2012–2013Based in Hopewell Junction, NY, US· patent location history
2013Patents assigned to ARVIN CHARLES L (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 18 | 1999–2014 |
| LIU HSICHANGself | 3 | 2012–2013 |
| NATARAJAN GOVINDARAJAN | 2 | 2012 |
| WEISMAN RENEE L | 2 | 2012–2013 |
| ARVIN CHARLES L | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Fishkill, New York, US | 16 | 1999–2014 |
| Hopewell Junction, New York, US | 2 | 2012–2013 |